Differential reference voltage generator for NMOS single-supply integrated circuits
First Claim
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1. Differential reference voltage generator for NMOS single-supply integrated circuits, characterized in that it comprises:
- Power SupplyA first MOS depletion transistor (MD1) Have a first gate and a first source connected together, and a first drain connected with said power supply (VDD);
a second MOS depletion transistor (MD2) have a second drain connected with said power supply and a second gate connected with said first source of the first transistor and having a second source;
a third MOS enhancement transistor (ME1) have a third drain and a third gate connected together and with said first source of the first transistor and having a third source;
a fourth MOS enhancement transistor (ME2) having a fourth drain and a fourth drain and gate connected together and with said second source of the second transistor;
a fifth MOS enhancement transistor (ME3) having a fifth drain and a fifth gate connected together and with said third source of the third transistor and having a fifth source being grounded;
a sixth MOS enhancement transistor (ME4) having a sixth drain connected with said fourth source of the fourth transistor having a sixth source grounded; and
having a sixth gate connected with said fifth gate of the fifth transistor;
differential reference voltage being the difference between the voltage present at said second source of the second transistor (MD2) and that present at the gate of the fifth and sixth transistor (ME3, ME4).
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Abstract
Voltage reference is generated by a current generator which, through a current-mirror amplifier, biases an enhancement MOS transistor as well as a depletion one, so that the desired voltage is equal to the difference between their threshold voltages.
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Citations
2 Claims
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1. Differential reference voltage generator for NMOS single-supply integrated circuits, characterized in that it comprises:
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Power Supply A first MOS depletion transistor (MD1) Have a first gate and a first source connected together, and a first drain connected with said power supply (VDD); a second MOS depletion transistor (MD2) have a second drain connected with said power supply and a second gate connected with said first source of the first transistor and having a second source; a third MOS enhancement transistor (ME1) have a third drain and a third gate connected together and with said first source of the first transistor and having a third source; a fourth MOS enhancement transistor (ME2) having a fourth drain and a fourth drain and gate connected together and with said second source of the second transistor; a fifth MOS enhancement transistor (ME3) having a fifth drain and a fifth gate connected together and with said third source of the third transistor and having a fifth source being grounded; a sixth MOS enhancement transistor (ME4) having a sixth drain connected with said fourth source of the fourth transistor having a sixth source grounded; and
having a sixth gate connected with said fifth gate of the fifth transistor;differential reference voltage being the difference between the voltage present at said second source of the second transistor (MD2) and that present at the gate of the fifth and sixth transistor (ME3, ME4). - View Dependent Claims (2)
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Specification
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Current AssigneeCSELT Centro Studi e Laboratori Telecomunicazioni SpA (Telecom Italia S.p.A.)
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Original AssigneeCSELT Centro Studi e Laboratori Telecomunicazioni SpA (Telecom Italia S.p.A.)
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InventorsSalerno, Franco, Sartori, Mario
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Primary Examiner(s)Wong, Peter S.
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Application NumberUS06/779,087Time in Patent Office557 DaysField of Search323/313, 323/314, 323/315, 323/907, 307/296 R, 307/297, 307/304US Class Current323/313CPC Class CodesG05F 3/245 producing a voltage or curr...
