Multi-user serial data bus

• US 4,654,655 A
• Filed: 03/02/1984
• Issued: 03/31/1987
• Est. Priority Date: 03/02/1984
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kowalski, Joseph L.
• Primary Examiner(s): Yusko, Donald J.
• Application Number:
  US06/585,753
• Time in Patent Office: 1,124 Days
• Field of Search: 340/825.5, 340/825.52, 340/825.51, 370/85, 370/91-93, 455/78, 455/14, 179/41 A
• US Class Current: 710/114
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 12/40019 Details regarding a bus master
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/4013 Management of data rate on the bus systems modifying transmission characteristics according to link quality H04L1/0001
• CPC Class Codes: H04L 12/40176 involving redundancy error detection or correction of the data by redundancy in hardware using active fault-masking in interconnections G06F11/2002; error detection or correction of the data by redundancy in hardware using active fault-masking in storage systems using spares or by reconfiguring G06F11/2053
• CPC Class Codes: H04W 88/02 Terminal devices

Abstract

A multiple device serial data bus and signalling scheme is described. The serial data bus allows for inter-peripheral communication at a data rate established by a bus control unit. Clocking information is extracted from data communicated from the bus controller to the peripheral devices. Additional conductors for clock information are not required. In addition an arbitration scheme is provided to eliminate bus contention if several units request service simultaneously. The multiple device serial data bus is utilized on an as required basis and may communicate information at a variety of data rates.

Claims

1. A data communications system, comprising:

(a) a serial data bus including at least first and second conductors;

(b) a plurality of peripheral units each having a multi-bit pre-assigned address indicative of a pre-assigned priority and including means coupled to said serial data bus for placing a first bit of its pre-assigned address on said first conductor and the remaining bits of its pre-assigned address on said first conductor in response to clocking information on said second conductor, means for detecting addresses placed on said first conductor, and means for releasing said first conductor in response to detection of an address having a having priority than its pre-assigned address; and

(c) a bus control unit coupled to said serial data bus for detecting peripheral unit addresses placed on said first conductor and placing the clocking information on said second conductor in response thereto.

2. The data communication system according to claim 1, wherein said serial data bus further includes a third conductor, said bus control unit being coupled to said second and third conductors for placing a read/write bit, the pre-assigned address of a destination peripheral unit, and an information word on the second and third conductors according to a predetermined signalling scheme, and said peripheral units each including means coupled to said second and third conductors for detecting said read/write bit, its pre-assigned address in response to detection of said read/write bit, and the information word in response to detection of its pre-assigned address.

3. The data communication system according to claim 1, wherein said bus control unit has a pre-assigned multi-bit address indicative of the highest priority.

4. A peripheral unit coupled by a serial data bus to a control unit of a data communications system, each peripheral unit having a multi-bit pre-assigned address indicative of a pre-assigned priority, said serial data bus including at least first and second conductors, and said bus control unit coupled to said serial data bus for detecting peripheral unit addresses placed on said first conductor and placing clocking information on said second conductor in response thereto, said peripheral unit comprising:

means coupled to said serial data bus for placing a first bit of its pre-assigned address on said first conductor and the remaining bits of its pre-assigned address on said first conductor in response to the clocking information on said second conductor;

means for detecting addresses placed on said first conductor;

and means for releasing said first conductor in response to detection of an address having a higher priority than its pre-assinged address.

5. A data communications system, comprising:

(a) a serial data bus including at least first, second and third conductors;

(b) a plurality of peripheral units each having a multi-bit pre-assigned address indicative of a pre-assigned priority and including means coupled to said serial data bus for placing a first bit of its pre-assigned address on said first conductor and the remaining bits of its pre-assigned address on said first conductor in response to clocking information on at least one of said second and third conductors, means for detecting addresses placed on said first conductor, and means for releasing said first conductor in response to detection of an address having a higher priority than its pre-assigned address; and

(c) a bus control unit coupled to said serial data bus for detecting peripheral unit addresses placed on said first conductor and placing the clocking information on said one of said second and third conductors in response thereto.

6. The data communication system according to claim 5, wherein said bus control unit is coupled ot said second and third conductors for placing a read/write bit, the pre-assigned address of a destination peripheral unit, and an information word on the second and third conductors according to a predetermined signalling scheme, and said peripheral units each including means coupled to said second and third conductors for detecting said read/write bit, its pre-assigned address in response to detection of said read/write bit, and the information word in response to detection of tis pre-assigned address.

7. The data communication system according to claim 5, wherein said bus control unit has a pre-assigned multi-bit address indicative of the highest priority.

8. A peripheral unit coupled by a serial data bus to a control unit of a data communications system, each peripheral unit having a multi-bit pre-assigned address indicative of a pre-assigned priority, said serial data bus including at least first, second and third conductors, and said bus control unit coupled to said serial data bus for detecting peripheral unit addresses placed on said first conductor and placing clocking information on at least one of said second and third conductors in response thereto, said peripheral unit comprising:

means coupled to said serial data bus for placing a first bit of its pre-assigned address on said first conductor and the remaining bits of its pre-assigned address on said first conductor in response to the clocking information on said one of said second and third conductors;

means for detecting addresses placed on said first conductor;

and means for releasing said first conductor in response to detection of an address having a higher priority than its pre-assigned address.

9. A method for controlling access to a serial data bus having at least first and second conductors for coupling a bus control unit to a plurality of peripheral units each having a multi-bit pre-assigned address indicative of a pre-assigned priority, said bus control unit coupled to said serial data bus for detecting peripheral unit addresses placed on said first conductor and placing clocking information on said second conductor in response thereto, said method of access for each peripheral unit comprising the steps of:

(a) placing a first bit of the pre-assigned address on the first conductor to request service;

(b) placing the remaining bits of the pre-assigned address on the first conductor in response to clocking information on the second conductor from the bus control unit;

(c) monitoring the first conductor to detect the address of a higher priority peripheral device; and

(d) releasing the first conductor if a higher priority peripheral device has requested service on the bus.

10. The method according to claim 9, wherein said placing step (c) further includes the steps of:

placing bits of the pre-assigned address of a destination peripheral unit on the first conductor; and

placing bits of an information word on the first conductor.

11. The method according to claim 10, further including for each peripheral unit not accessing the serial data bus the steps of:

monitoring the first conductor to detect its pre-assigned address; and

detecting the information word on the first conductor in response to detection of its pre-assigned address.

12. The method according to claim 9, wherein said bus control unit has a pre-assigned multi-bit address indicative of the highest priority.

13. The method according to claim 9, further including the steps of:

for said bus control unit;

placing a read/write bit on the second conductor to indicate information will follow from said bus control unit;

placing bits of the pre-assigned address of a destination peripheral unit on the second conductor; and

placing bits of an information word on the second conductor; and

for each peripheral unit not accessing the serial data bus;

monitoring the second conductor to detect said read/write bit;

monitoring the second conductor to detect its pre-assigned address in response to detection of said read/write bit; and

detecting the information word on the second conductor in response to detection of its pre-assigned address.