Analog signal conditioning and digitizing integrated circuit

• US 4,654,815 A
• Filed: 02/07/1985
• Issued: 03/31/1987
• Est. Priority Date: 02/07/1985
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tan, Khen-Sang, Marin, James S.
• Primary Examiner(s): Ruggiero, Joseph
• Application Number:
  US06/699,516
• Time in Patent Office: 782 Days
• Field of Search: 364/600, 364/602, 364/604, 364/606, 364/607, 364/608, 340/347 M, 340/347 AD, 340/347 DA, 340/347 CC, 340/347 SH
• US Class Current: 708/7
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: H03M 1/1047 using an auxiliary digital/analogue converter for adding the correction values to the analogue signal H03M1/1052 takes precedence

Abstract

An analog signal conditioning and digitizing integrated circuit is provided having a multiplying digital to analog converter means (MDAC) including a gain capacitor array and an offset capacitor array, an operational amplifier, a feedback circuit including a feedback capacitor and a feedback clamping transistor, the operational amplifier and feedback circuit connected to the gain and offset capacitor arrays for setting the gain and the amount of offset correction of the MDAC, a correlated double sample circuit including a series capacitor connected to the operational amplifier and a series clamping transistor connected to the junction of the series capacitor and a buffer amplifier for sampling the noise to be substracted and/or nulled across the series capacitor, and an analog to digital converter operatively connected to the MDAC for digitizing the output of the MDAC. In other embodiments the integrated circuit has separate bond pads for the analog signal inputs and outputs of the MDACs and DACs or for implementing feedback/feedforward discrete time transfer functions.

Claims

1. An analog signal conditioning and digitizing circuit means comprising an integrated circuit having a channel including a multiplying digital to analog converter, for providing gain adjustment and offset correction to an input voltage and an analog to digital converter operatively connected to the multiplying digital to analog converter for sampling, holding and digitizing the input voltage, said multiplying digital to analog converter comprising a summing and inverting negative feedback amplifier means for gain adjustment and offset noise correction and a correlated double sample circuit means connected to the amplifier means for subtracting or nulling sampled noise of the amplifier.

2. An analog signal conditioning and digitizing circuit means according to claim 1 wherein said integrated circuit includes a plurality of said channels and a tri-state bus operatively shared by the plurality of channels for providing a digital multiplexing capability.

3. An analog signal conditioning and digitizing circuit means according to claim 1 wherein the summing and inverting negative feedback amplifier comprises a gain capacitor array means, an offset capacitor array means, an operational amplifier and a feedback means, the operational amplifier and feedback means operatively connected to the gain capacitor array means and the offset capacitor array means.

4. An analog signal conditioning and digitizing circuit means according to claim 3 wherein the gain capacitor array means and offset capacitor array means each include a plurality of capacitors having binary number code related capacitance values, the gain and offset capacitor arrays each having a plurality of capacitors having first and second plates, the first plates of each array being connected in common, a plurality of switches operatively connected to the second plates of each array of capacitors for switching between a signal input and a reference voltage, control logic means and coefficient register connected to the plurality of switches for selectively switching the switches whereby the gain of the multiplying digital to analog converter is set by the sum of the capacitance values connected to the input voltage divided by the value of the feedback means and the amount of offset is set by the sum of the capacitance value connected to the multiplying digital to analog converter divided by the value of the feedback means.

5. An analog signal conditioning and digitizing circuit means according to claim 4 wherein the feedback means includes a feedback capacitor operatively connected to the operational amplifier whereby the value of the feedback means is the capacitance of the feedback capacitor.

6. An analog signal conditioning and digitizing circuit means according to claim 5 wherein the feedback means further includes a feedback clamp transistor operatively connected to the operational amplifier and feedback capacitor for periodically resetting the multiplying digital to analog converter and correcting drifts that occur from charge leakage off the capacitor arrays and feedback capacitor.

7. An analog signal conditioning and digitizing circit means according to claim 1 wherein the correlated double sample circuit comprises a series capacitor and a series clamp transistor operatively connected to the summing and inverting negative feedback amplifier means for subtracting or nulling the sampled noise across the series capacitor.

12. An analog signal conditioning and digitizing circuit means according to claim 1 wherein the integrated circuit further includes separate bond pads for the analog signal inputs and outputs of the MDACs and ADCs.

13. An analog signal conditioning and digitizing circuit according to claim 2 wherein the integrated circuit plurality of ADCs and DACs are tied to a common digital bus for providing a feedforward discrete time transfer function.

14. An analog signal conditioning and digitizing circuit according to claim 1 wherein the integrated circuit MDAC and ADC are operatively connected to provide a feedback time domain transfer function.

8. An analog signal conditioning and digitizing circuit means comprising an integrated circuit having a channel including a multiplying digital to analog converter, for providing gain adjustment and offset correction to an input voltage and an analog to digital converter operatively connected to the multiplying digital to analog converter for sampling, holding and digitizing the input voltage, said analog to digital converter means including a sample and hold and conversion means, a comparator means, an offset correction circuit, a successive approximation register, and a serial shift register, the sample and hold and conversion means for sampling and holding an input voltage during conversion, the comparator means operatively connected to the sample and hold and conversion means and offset correction circuit for comparing the output of the sample and hold and conversion means to the output of the offset correction circuit means, the successive approximation register operatively connected to the serial shift register for receiving and sequencing a bit through the sample and hold and conversion means and to the output of the comparator for performing a testing and/or reset operation and outputting a final state.

9. An analog signal conditioning and digitizing circuit means according to claim 8 wherein the analog to digital converter means includes a capacitor array for sampling and holding a charge in the array during conversion, a plurality of switches operatively connected to the capacitor array for selectively switching an isolated plate of each capacitor between analog ground and a reference voltage for conversion and charging the common plate of the capacitor array for comparison by the comparator with the offset correction circuit after each switch of the switches and selectively resetting or leaving set the switches.

10. An analog signal conditioning and digitizing circuit according to claim 9 wherein the capacitor array is an array of switching transistors.

11. An analog signal conditioning and digitizing circuit means according to claim 8 further including an output register operatively connected to the successive approximation register for holding the result of a previous conversion while allowing the start of a successive conversion prior to transfer of the prior comparison to external logic circuits.