Apparatus for automatically correcting erroneous data and for storing the corrected data in a common pool alternate memory array

• US 4,654,847 A
• Filed: 12/28/1984
• Issued: 03/31/1987
• Est. Priority Date: 12/28/1984
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines SA (International Business Machines Corporation)
• Inventors: Dutton, Patrick F.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Beausoliel, Jr., Robert W.
• Application Number:
  US06/687,401
• Time in Patent Office: 823 Days
• Field of Search: 371/10, 371/38, 365/200, 364/200, 364/900
• US Class Current: 714/6.1
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring

Abstract

An apparatus is disclosed which detects the existence of an error, in a computer system, corrects the error, and takes steps to ensure that the error will never again re-occur. The error resides in the integrity of data stored in a main memory. When the data is read from memory and found to be erroneous, the data is corrected and stored in a spare portion of a small alternate memory array. In addition, the identity of the corrected data is also stored in the alternate memory array. During a subsequent read of the data from the main memory, the alternate memory array is simultaneously consulted. The identity of the corrected data, stored in the alternate memory array, is compared with the incoming address, and the corrected data is read from the spare portion of the alternate memory array. As a result, the erroneous data is not reproduced during a subsequent read of the data from the main memory.

Claims

1. A microprocessor controlled apparatus for reading data from a main memory means, for detecting the existence of a double bit error in said data, for correcting said double bit error without the use of spare memory chips, and for ensuring that said error will not be reproduced during a subsequent read of said data, comprising:

said main memory means for storing said data therein, said data including erroneous and non-erroneous data;

detection means, connected to said main memory means, for detecting the existence of a double bit error in said data read from said main memory means;

first correction means, connected to said microprocessor, for correcting a single bit error of said double bit error detected by said detection means thereby producing partially corrected data and for developing an output signal indicative of said partially corrected data;

common pool alternate memory array means, connected to said detection means and responsive to said output signal developed from said first correction means, for storing said partially corrected data, received from said first correction means,

said partially corrected data being simultaneously accessed from said common pool alternate memory array means when said data is accessed from said main memory means,

thereby changing said double bit error into a remaining single bit error; and

second correction means, connected to said detection means, for correcting said remaining single bit error.

2. The apparatus of claim 1, wherein said second correction means is also for correcting all single bit errors detected by said detection means directly without utilizing said common pool alternate memory array means and said first correction means.