Multi-trigger logic analyzer

• US 4,654,848 A
• Filed: 04/02/1985
• Issued: 03/31/1987
• Est. Priority Date: 04/06/1984
• Status: Expired due to Fees

• Current Assignee: Takeda Riken Kogyo Kabushiki Kaisha
• Original Assignee: Takeda Riken Kogyo Kabushikikaisha
• Inventors: Noguchi, Kazuo
• Primary Examiner(s): Harkcom, Gary V.
• Application Number:
  US06/719,154
• Time in Patent Office: 728 Days
• Field of Search: 371/15-16, 371/20-21, 371/24-26, 371/29, 371/67, 324/73 R, 324/73 AT, 324/73 PC
• US Class Current: 714/724
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers

Abstract

Logic data (input data) is sequentially supplied to a data memory using sampling pulses and the input data is written into the data memory at an address specified by an address signal from an address counter which advances by one upon each occurrence of the sampling pulse. The input data and an output trigger word from a trigger word register are compared by a trigger word detector, and when coincidence is detected therebetween, a coincidence signal is generated, which signal is delayed by a delay circuit by a value corresponding to output delay data from a delay register. The delayed output is provided as a stop signal. By the stop signal the address counter is preset to a leading address of a storage area of the data memory into which data is to be stored and the next trigger word is provided from the trigger register. Further, the next delay data is provided from a delay register and the next store number is output from a store-number register. The sampling pulses are counted by a store-number counter, and when the count value coincides with the output store number from the store-number register before the stop signal is generated, the address counter is preset to the leading address of the storage area of the data memory into which data is being written at that time.

Claims

1. A logic analyzer comprising:

a sampling pulse generator for outputting a sampling pulse;

a temporary memory for sampling input digital data in response to the sampling pulse and for temporarily holding the sampled data;

an address counter advancing by one upon each occurrence of the sampling pulse, for generating an address signal;

a data memory addressed by the address signal from the address counter, for writing at the specified address the data held in the temporary memory, said data memory being divided into a plurality of storage areas;

a store-number register for storing and outputting at least one store number indicating the number of data that can be stored in each of said plurality of storage areas of said data memory;

a store-number counter supplied with the respective store number output from the store-number register, for counting the sampling pulses and for generating a respective output signal when the count corresponds to the store number;

a trigger word register for storing and outputting a plurality of trigger words respectively corresponding to the storage areas of the data memory;

a trigger word detector for comparing the data held by the temporary memory and the respective trigger word output from the trigger word register and, when detecting coincidence therebetween, for generating a coincidence signal;

a delay means for delaying the coincidence signal from the trigger word detector for a predetermined period of time, and for generating a corresponding stop signal;

a leading address generator supplied with each respective store number from the store-number register, for generating, when supplied with the stop signal from the delay means, a leading address of the respective storage area of the data memory to be accessed next, and for holding and outputting the leading address of the currently accessed storage area of the data memory until supplied with the stop signal;

means for presetting, by the output signal from the store-number counter, the respective leading address held in the leading address generator into the address counter and for presetting in the address counter, responsive to the stop signal from the delay means, the next leading address generated in the leading address generator; and

a trigger word select means for selecting the respective trigger word for output from the trigger word register upon each occurrence of the stop signal from the delay means.

2. A logic analyzer according to claim 1 wherein a plurality of store numbers are stored in the store-number register, and which includes a store-number select means for selecting one of the store numbers for output upon each occurrence of the stop signal from the delay means.

3. A logic analyzer according to claim 2, wherein the delay means includes a delay register for storing delay data respectively corresponding to a plurality of a delay times, and a delay time select means for selecting, upon each occurrence of the stop signal from the delay means, one of the delay data for output to the delay means to cause the coincidence signal to be delayed for a predetermined period of time.

4. A logic analyzer according to claim 3 wherein the trigger word select means selects a different trigger word for each selection, the store-number select means selects a different store number for each selection and the delay time select means selects a different delay data for each selection.

5. A logic analyzer according to claim 1 which further includes a delay register for storing delay data respectively corresponding to a plurality of delay times, and a delay time select means for selecting, upon each occurence of the stop signal from the delay means, one of the delay data for output to the delay means to cause the coincidence signal to be delayed for a predetermined period of time.

6. A logic analyzer according to any one of claims 1 to 5 wherein the store-number counter is a presettable counter and presets therein the output of the store-number register by the stop signal from the delay means and the count-up signal from the store-number counter.

7. A logic analyzer according to any one of claims 1 to 5, comprising a latch circuit and an adder, wherein the leading address generator adds the output of the store-number register and the output of the latch circuit by said adder, latches the adder output in the latch circuit by the stop signal from the delay means, and outputs it as the leading address of the storage area to be accessed next.

8. A logic analyzer according to any one of claims 1 to 5, comprising a control unit for selectively reading out from each said address of the data memory said data written therein and for displaying the read-out data on a display.

9. A logic analyzer according to claim 8 wherein the control unit includes means for processing the read-out data and for supplying a corresponding output to the display for said displaying.