Self-aligned recessed gate process

• US 4,656,076 A
• Filed: 04/26/1985
• Issued: 04/07/1987
• Est. Priority Date: 04/26/1985
• Status: Expired due to Fees

• Current Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Original Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Inventors: Gleason, Kimberly R., Vetanen, William A., Beers, Irene G.
• Primary Examiner(s): Kittle, John E.
• Assistant Examiner(s): RYAN, PATRICK J
• Application Number:
  US06/727,484
• Time in Patent Office: 711 Days
• Field of Search: 430/312, 430/313, 430/314, 430/315, 430/316, 430/317, 430/319, 430/323, 430/324, 430/329, 29/576 B, 29/576 C, 29/578, 148/1.5, 148/187, 428/137, 428/330, 428/901
• US Class Current: 428/137
• CPC Class Codes: H01L 29/0843 Source or drain regions of field-effect devices
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66871 Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
• CPC Class Codes: Y10S 428/901 Printed circuit
• CPC Class Codes: Y10T 428/24322 Composite web or sheet
• CPC Class Codes: Y10T 428/258 Alkali metal or alkaline earth metal or compound thereof

Abstract

An integrated circuit gate process and structure are disclosed which provide a self-aligned, recessed gate enhancement-mode GaAsFET. The process includes making self-aligned implants prior to gate metallization, with an intermediate step of applying patches of plasma- and chemical-etch resistant dielectric, such as zirconium oxide (ZrO), over the self-aligned implants to fixedly define gate length. The self-aligned gate process includes stair-stepping three successive implants, in respect to both depth and concentration, to provide a dopant concentration gradient inclined depthwise away from each side of the gate. The self-aligned, recessed gate GaAsFET exhibits improved source-gate resistance without degradation of gate-drain capacitance, increased gain and drain-source current, and reduced knee-voltage. Gate length is minimized to the limits of photolithography without degrading input resistance.

Claims

1. A self-aligned gate process for fabricating an integrated circuit device comprising:

providing a substrate having a reference surface, the substrate being composed of a material etchable by a first etchant;

implanting ions to form an active device region within the substrate extending to a first predetermined depth below said surface;

masking the reference surface over the active device region with an ion-opaque, removable first mask layer;

forming a pair of spaced-apart openings in the mask within the active device region;

implanting ions through the pair of openings into the active device region to form a pair of self-aligned implant regions spaced apart about a gap having a first length defined by the spacing of the openings;

depositing a dielectric layer through the mask openings onto the substrate so as to cover the self-aligned implant regions, the dielectric layer being composed of a first dielectric material resistant to said first etchant;

removing the first mask layer and any of the said dielectric material deposited thereon while leaving two spaced-apart patches of the dielectric material covering the self-aligned implant regions and aligned therewith;

masking the reference surface and the two patches of dielectric material with a second mask layer;

forming an opening in the second mask layer in a location and of a second length encompassing at least a portion of said gap and overlapping an adjoining portion of at least one of the two patches;

etching the substrate material through the opening in the second mask to form a recess in said active region having a second predetermined depth less than said first depth and a length at said reference surface that is defined by the gap between the two patches of dielectric material; and

depositing a gate conductor material through the opening in the second mask to form a gate having a gate contact in contact with the substrate material within the gap, the gate contact having a maximum length defined by said recess.

2. A gate process according to claim 1 in which the substrate material includes GaAs and the first dielectric material includes ZrO.

3. A gate process according to claim 1, including:

prior to the first masking step, depositing on the substrate reference surface a preliminary dielectric layer composed of a second dielectric material etchable by a second etchant, the first dielectric material being resistant thereto; and

prior to etching the substrate material, etching the preliminary dielectric layer through the opening in the second mask to expose the substrate material.

4. A gate process according to claim 3 in which the first material is GaAs;

the second material is Si₃ N₄ ; and

the third material includes ZrO.

5. A gate process according to claim 1 including sizing the opening in the second mask layer so that the second length is greater than the first length.

6. A gate process according to claim 1 including annealing the substrate prior to the step of depositing gate material.

7. A gate process according to claim 1 including selecting for said dielectric layer and for said substrate, materials having approximately equal coefficients of thermal expansion.

8. A gate process according to claim 1 including:

selecting for said substrate material a crystalline material having a crystallographic structure which said first etchant etches anisotropically;

selecting as said reference surface a face of the material such that the material etches at a non-normal inclination to the reference surface; and

orienting the gate on the reference surface so that the recess is formed with opposite sides inclined inward proceeding depthwise into the substrate so as to space the gate conductor material away from the gate implant regions at said predetermined depth.

9. A gallium arsenide (GaAs) integrated circuit gate structure, comprising:

a GaAs substrate having a reference surface;

a first region within the substrate doped to a first dopant concentration and a first depth;

a second region, adjoining the first region within the substrate, doped to a second dopant concentration greater than the first concentration and defining a dopant gradient boundary extending depthwise into the substrate from the reference surface;

a dielectric layer covering a portion of the substrate surface including the second doped region and having an edge aligned with said dopant gradient boundary;

means defining a channel aligned with said edge and recessed depthwise into the substrate in the first doped region to a second depth less than the first depth; and

conductive gate material filling the channel;

the channel having a sidewall aligned at the reference surface with the edge of the dielectric layer and with the dopant gradient boundary.

10. A GaAs gate structure according to claim 9 in which the sidewall of the channel is inclined inwardly proceeding downward so as to space the conductive gate material away from the gradient boundary.

11. A gate structure according to claim 9 including a third region within the substrate, doped to a third concentration greater than the first and second concentrations and spaced apart from the dopant gradient boundary and the first region.

12. A self-aligned gate process for making integrated circuits, comprising

providing a semi-insulating substrate having a reference surface;

doping a first defined area of the substrate to a first dopant concentration and a first depth;

doping a pair of second defined areas of the substrate overlapping the first defined area and spaced apart therein at a first spacing, to a second concentration and a second depth that are greater than the concentration and depth of doping in the first area;

doping a pair of third defined areas of the substrate, overlapping the second areas within the first area and spaced apart therein to define inward boundaries at a second spacing less than the first spacing, to a third concentration intermediate the first and second concentration and a depth intermediate the first and second depth;

depositing a dielectric layer atop the substrate, solely over the third areas so as to define two dielectric patches having a gap between them which is aligned with said inward boundaries;

masking the substrate with a mask layer and forming an opening in the mask layer encompassing at least a portion of said gap; and

depositing a conductive gate material through the opening to form a gate contact within the gap.

13. A method according to claim 12 including:

composing the dielectric patches of zirconium oxide;

depositing a plasma-etchable dielectric layer over said surface prior to doping said first defined area; and

plasma etching the plasma-etchable dielectric through the opening in the mask layer;

the zirconium oxide patches confining the plasma etch to the gap within said inward boundaries.

14. A method according to claim 12 including selectively etching a recess in the substrate within the gap, the dielectric patches being composed of an etch-resistant dielectric material.

15. A method according to claim 12 including:

depositing a first dielectric layer over said surface prior to doping said first defined area;

depositing a third dielectric layer over said substrate including over said first, second and third areas, the first and third dielectric layers each being formed of a dielectric material removable by a predetermined etchant and the dielectric patches being formed of a different dielectric material resistant to said etchant;

etching through the opening with said predetermined etchant to remove portions of the first and third dielectric layers exposed within said gap and thereby expose a portion of the reference surface of the substrate within the gap; and

etching the exposed portion of the substrate surface so as to form a recess, the substrate in the gap having a predetermined depth from the reference surface.

16. A self-aligned gate process for making integrated circuits, comprising:

providing a semi-insulating substrate having a reference surface;

depositing a first dielectric layer over said surface;

applying a layer of photoresist over the first dielectric layer and forming a pair of closely spaced apart openings extending through the photoresist to expose a surface portion of the first dielectric layer through said openings;

implanting ions through the photoresist openings into the substrate to define two implanted regions having implant boundaries substantially aligned with said openings and spaced apart to define a gap between the regions;

depositing a second dielectric layer on the photoresist and within the openings atop the surface portion of the first dielectric layer exposed therein;

removing the layer of photoresist, thereby removing the second dielectric layer deposited thereon and leaving a pair of areas of the second dielectric layer atop the first dielectric layer extending over the pair of implanted regions and having dielectric boundaries spaced closely apart in alignment with said implant boundaries to define a gap in accordance with the spacing of the openings; and

etching within said gap with a first predetermined etchant selectively to remove the first dielectric layer and thereby expose a portion of the substrate bounded by the boundaries of said second dielectric layer; and

depositing a conductive gate material within the gap and the recess to form a gate contact;

the second dielectric layer being composed of a material which is non-etchable by the first etchant so that the gate contact is aligned with the implant boundaries in accordance with the closely-spaced-apart openings in the photoresist.

17. A method according to claim 16 including:

implanting ions into a region of the substrate including said gap, prior to applying the layer of photoresist, to a first depth below the reference surface; and

etching the exposed portion of the substrate surface with a second predetermined etchant so as to form a recess in the substrate within the gap having a depth less than the first depth for producing a predetermined pinch-off voltage;

the second dielectric layer material being resistant to the second etchant.

18. A method according to claim 17 including selecting a substrate having a crystallographic structure in the reference surface which the second etchant etches anisotropically and orienting the gate on the reference surface so that the recess is etched to form nonparallel opposite sides which are inclined toward one another and away from the second defined doped areas proceeding depthwise into the substrate.

19. A method according to claim 16 including selecting as said second dielectric layer material a material having a thermal coefficient of expansion approximately equal to a coefficient of expansion of the substrate and following removal of the layer of photoresist and, prior to deposition of conductive gate material, annealing the substrate to heal defects resulting from implanting and to activate the implanted ions.

20. A method according to claim 16 wherein the substrate is gallium arsenide, the first dielectric is Si₃ N₄ and the second dielectric is ZrO.