Speed up of up-going transition of TTL or DTL circuits under high _capacitive load

• US 4,656,367 A
• Filed: 10/18/1985
• Issued: 04/07/1987
• Est. Priority Date: 10/18/1985
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Van Goor, Kenneth A., Schettler, Helmut, Pritzlaff, Philip E. Jr., Culican, Edward F.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Wambach, M. R.
• Application Number:
  US06/789,250
• Time in Patent Office: 536 Days
• Field of Search: 307/443, 307/454, 307/456, 307/270, 307/254, 307/300
• US Class Current: 326/90
• CPC Class Codes: H03K 19/0136 by means of a pull-up or down element
• CPC Class Codes: H03K 19/088 Transistor-transistor logic

Abstract

A circuit for enhancing the ability of digital circuits to drive highly capacitive loads is disclosed. The circuit has particular utility when employed with logic circuits such as "TTL" (Transistor-Transistor Logic) and "DTL" (Diode-Transistor Logic).

Claims

1. In an integrated circuit chip, said integrated circuit chip comprising:

at least first and second binary logic circuits, each of said at least first and second binary logic circuits having an input and an output;

a highly capacitive load circuit, said load circuit having an input;

said integrated circuit chip being characterized by the inclusion of a speedup circuit coupled between a common connection of said outputs of said at least first and second binary logic circuits and said highly capacitive load, said speed-up circuit comprising;

first, second, third and fourth transistors, each of said first, second, third and fourth transistors having an emitter, base and collector,

said collector of said first transistor, said base of said first transistor and said base of said second transistor connected in common,

a first resistor connected between a source of potential and said collector of said first transistor,

a second resistor connected between said source of potential and a common connection of said emitter of said third transistor, said base of said third transistor and said base of said fourth transistor,

said collector of said second transistor connected to said source of potential,

said emitter of said first transistor and said emitter of said fourth transistor connected in common to said outputs of said at least first and second binary logic circuits, and

said emitter of said second transistor, said collector of said third transistor and said collector of said fourth transistor connected in common to said input of said highly capacitive load.

2. In an integrated circuit chip, as recited in claim 1, wherein said at least first and second binary logic circuits and said highly capacitive load circuit are respectively binary logic circuits of the TTL technology family.

3. In an integrated circuit chip, as recited in claim 2, wherein said at least first and second binary logic circuits and said highly capacitive load circuit are respectively binary logic circuits of the DTL technology family.

4. In an integrated circuit chip, as recited in claims 1 or 2, wherein at least said binary logic circuits connected to the input of said speed-up circuit include passive pull-up circuit means.

5. In an integrated circuit chip, as recited in claims 1 or 2, wherein at least said binary logic circuits connected to the input of said speed-up of circuit include passive pull-up circuit means comprising at least one resistor.