High-speed voltage level shift circuit

• US 4,656,373 A
• Filed: 11/26/1984
• Issued: 04/07/1987
• Est. Priority Date: 11/26/1984
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: RCA Corporation
• Inventors: Plus, Dora
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Bertelson, David R.
• Application Number:
  US06/674,845
• Time in Patent Office: 862 Days
• Field of Search: 307/264, 307/475, 307/270, 307/290, 307/279, 307/450, 307/451, 307/576, 307/579, 307/585, 307/605, 365/104, 365/226
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

An input signal translating circuit includes first and second transistors having their conduction paths connected in series between a first power terminal and an output node, and a third transistor whose conduction path is connected between the output node and a second power terminal. The circuit includes means for applying an input signal to the control electrodes of the first and third transistors for turning one on and the other off for one value of the input signal and turning the one off and the other on for another value of input signal. Means responsive to the signal produced at the output node generate a delayed negative feedback signal which is applied to the control electrode of the second transistor for turning-it-off after the voltage at said output node is at, close to, or greater than, the voltage applied to the first power terminal and for turning-it-on after the voltage at said output node is at, or close to, the voltage at the second power terminal.

Claims

1. The combination comprising:

first and second power terminals for the application thereto of first and second different operating voltages, respectively;

a first node for the application thereto of signals varying in amplitude between said first and said second operating voltages;

first, second and third transistors, each transistor having a conduction path and a control electrode for controlling the conductivity of said conduction path;

a second node for the production thereat of an output signal;

means connecting the control electrodes of said first and third transistors to said first node;

means connecting the conduction path of said third transistor between said second node and said first power terminal;

means connecting the conduction paths of said first and second transistors in series between said second node and said second power terminal; and

means responsive to the signal produced at said second node for generating a delayed negative feedback signal and for applying said delayed negative feedback signal to the control electrode of said second transistor for;

(a) turning-it-off and preventing current flow therethrough after the voltage at said second node is at, close to, or greater than, the voltage applied to said second power terminal; and

(b) turning-it-on and enabling current conduction therethrough after the voltage at said second node is at, or close to, the voltage at said first power terminal.

2. The combination as claimed in claim 1 wherein said first and second transistors are of one conductivity type and said third transistor is of complementary conductivity type.

3. The combination as claimed in claim 1 wherein said first transistor is of one conductivity type and second and third transistors are of complementary conductivity type.

4. The combination as claimed in claim 2 wherein said means responsive to the signal produced at said signal output node for generating and applying a delayed negative feedback signal to the control electrode of said second transistor includes:

(a) a third power terminal for the application thereto of an operating potential outside the range of the potential applied between said first and second power terminals;

(b) a latch circuit operatively connected between said first and third power terminals, said latch including an inverter connected at its signal input to said second node and connected at its output to a third node;

said latch further including a feedback transistor having its conduction path connected between said third power terminal and said second node and having its control electrode connected to said third node; and

(c) an inverting means operatively connected between said first and third power terminals and having a signal input connected to said third node and having a signal output connected to said control electrode of said second transistor.

5. The combination as claimed in claim 1 further including a fourth transistor of same conductivity type as said first transistor and a fifth transistor of same conductivity type as said third transistor, each one of said fourth and fifth transistors having a control electrode and a conduction path;

means connecting the conduction path of said fourth transistor in parallel with that of said first transistor;

a second input node;

means connecting the control electrodes of said fourth and fifth transistors to said second input node; and

wherein said means connecting the conduction path of said third transistor between said second node and said first power terminal includes the conduction path of said fifth transistor.

6. The combination comprising:

first and second power terminals for the application thereto of first and second different operating voltages, respectively;

a signal input terminal for the application thereto of signals varying in amplitude between said first and said second operating voltages;

first and second transistors of one conductivity type and a third transistor of second conductivity type, each transistor having a conduction path and a control electrode for controlling the conductivity of said conduction path;

a first signal output node;

means connecting the control electrodes of said first and third transistors to said signal input terminal;

means connecting the conduction path of said third transistor between said first signal output node and said first power terminal;

means connecting the conduction paths of said first and second transistors in series between said second power terminal and said first signal output node; and

means responsive to the signal produced at said first signal output node for generating and applying a delayed negative feedback signal to the control electrode of said second transistor for turning-it-off after the voltage at said output node is at, close to, or greater than, the voltage applied to said second power terminal and for turning-it-on after the voltage at said output node is at, or close to, the voltage at said first power terminal.

7. The combination as claimed in claim 6 wherein said means responsive to the signal at said first output node for generating and applying a delayed feedback signal to the control electrode of said second transistor includes:

a latch circuit having an input signal node connected to said first signal output node and an output connected to a second node;

inverting means having an input signal node connected to said second node and having an output connected to said control electrode of said second node; and

means for applying an operating potential across said latch circuit and said inverting means which is greater in amplitude than the potential applied between said first and second power terminals.

8. The combination as claimed in claim 7 wherein said latch circuit includes an inverter connected between said first signal output node and said second node, and positive feedback means coupling a signal back to said first signal output node for causing said inverter to latch.

9. The combination as claimed in claim 8 wherein said first, second and third transistors are insulated-gate field-effect transistors.

10. The combination comprising:

first, second and third power terminals for the application thereto of first, second, and third different operating voltages, respectively; and

wherein said second voltage is intermediate said first and third operating voltages;

a signal input terminal for the application thereto of signals varying in amplitude between said first and said second operating voltages;

first and second transistors of one conductivity type and a third transistor of second conductivity type, each transistor having a conduction path and a control electrode for controlling the conductivity of its conduction path;

a first signal output node;

means connecting the control electrodes of said first and third transistors to said signal input terminal;

means connecting the conduction path of said third transistor between said first signal output node and said first power terminal;

means connecting the conduction paths of said first and second transistors in series between said second power terminal and said first signal output node;

a latch circuit having at least one stable state, said latch having a signal input connected to said first signal output node and having a signal output connected to a second signal output node;

inverting means having a signal input connected to said second signal output node and having an output connected to the control electrode of said second transistor; and

means for operatively connecting said latch and said inverting means between said first and third power terminals.