Voltage comparison circuit with ripple component elimination
First Claim
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1. An amplification circuit comprising:
- a signal input terminal and signal output terminal;
amplifying means having input and output terminals and including a CMOS inverter having MOS transistors of different channel types, said output terminal being coupled to said signal output terminal;
at least one switching MOS transistor whose current path is connected between said signal input terminal and said output terminal of said amplifying means and whose gate is connected to receive a clock signal to set an operation point of said amplifying means; and
a first low-pass filter connected between said switching MOS transistor and said input terminal of said amplifying means;
a second low-pass filter connected between said switching transistor and said output terminal of said amplifying means; and
wherein each of said first and second low-pass filters includes a CR filter comprising a semiconductor substrate, an impuirty layer functioning as resistance means and capacitance means, said impurity layer having a conductivity type opposite to that of said semiconductor substrate and being formed in a surface area of said semiconductor substrate.
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Abstract
A voltage comparison circuit having an amplification circuit which includes an inverting amplifier and a switching MOS transistor for setting an operation point of the inverting amplifier connected between input and output terminals of the inverting amplifier. The amplification circuit further includes at least one low-pass filter connected in a closed loop including the inverting amplifier and the switching MOS transistor.
22 Citations
1 Claim
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1. An amplification circuit comprising:
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a signal input terminal and signal output terminal; amplifying means having input and output terminals and including a CMOS inverter having MOS transistors of different channel types, said output terminal being coupled to said signal output terminal; at least one switching MOS transistor whose current path is connected between said signal input terminal and said output terminal of said amplifying means and whose gate is connected to receive a clock signal to set an operation point of said amplifying means; and a first low-pass filter connected between said switching MOS transistor and said input terminal of said amplifying means; a second low-pass filter connected between said switching transistor and said output terminal of said amplifying means; and wherein each of said first and second low-pass filters includes a CR filter comprising a semiconductor substrate, an impuirty layer functioning as resistance means and capacitance means, said impurity layer having a conductivity type opposite to that of said semiconductor substrate and being formed in a surface area of said semiconductor substrate.
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Specification
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Current AssigneeTokyo Shibaura Denki Kabushiki Kaisha
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Original AssigneeTokyo Shibaura Denki Kabushiki Kaisha
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InventorsMasuda, Eiji, Matsuo, Kenji
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Primary Examiner(s)Miller, Stanley D.
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Assistant Examiner(s)Callahan, Timothy P.
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Application NumberUS06/455,797Time in Patent Office1,553 DaysField of Search307/350, 307/530, 307/352, 307/353, 307/355, 307/240, 307/279, 307/496, 307/542, 307/543, 307/451, 307/469, 307/520, 307/501, 330/51, 330/107, 330/264, 330/267, 328/128, 328/165, 328/149, 328/167US Class Current330/277CPC Class CodesH03K 5/249 using clock signals
