Device in the instruction unit of a pipeline processor for instruction interruption and repetition

• US 4,656,578 A
• Filed: 09/04/1984
• Issued: 04/07/1987
• Est. Priority Date: 09/16/1983
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Richter, Stephan, Getzlaff, Klaus J., Hajdu, Johann, Chilinski, Herbert
• Primary Examiner(s): Williams, Archie E.
• Assistant Examiner(s): CHAN, EMILY Y
• Application Number:
  US06/646,873
• Time in Patent Office: 945 Days
• Field of Search: 364/200, 364/900, 364/200 MS File
• US Class Current: 712/244
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

In the processing of instructions in data processing systems it is not always possible to execute these instructions without interruption since particular situations, in the following called events can occur which necessitate a short interruption for executing the operations caused by such events before continuing the interrupted instruction processing. Such repetition however is only possible when the contents of the operation register containing the instruction is frozen during the interruption. Such a situation requires two actions: the first is the execution of a forced operation to resolve the event. The second action is a repetition of the instruction and execution phase of the interrupted instruction.

Claims

1. In an instruction unit of a pipeline processor, a device means for interrupting an execution of an instruction in response to an occurrence of an event and for repeating the execution of said instruction following the resolution of said event, said event being characterized by the generation of an event signal, said device means comprising:

first operation register means for storing said instruction, said instruction being maintained in said first operation register means in response to said event signal;

first instruction cycle counter means for providing a count of machine cycles relating to the execution of said instruction stored in said first operation register means, the contents of said first instruction cycle counter means being maintained in response to said event signal;

second operation register means responsive to said event signal for storing further instructions and control information;

second instruction cycle counter means for providing a count of machine cycles relating to the execution of said further instruction stored in said second operation register means;

operation decoder means for decoding an instruction;

switch means interconnected between said operation decoder means and said first operation register means, said first instruction cycle counter means, said second operation register means and said second instruction cycle counter means and responsive to said event signal for transferring said further instructions and control information and said count from said second operation register means and said second instruction cycle counter means to said operation decoder means in response to said event signal.

2. The device means of claim 1, wherein said first operation register means comprises a first operation register and a second operation register, said switch means switching the contents of said second operation register to the output of said first operation register when said occurrence of event is terminated.

3. The device means of claim 2, wherein said operation decoder means comprises a first operation decoder and a second operation decoder, and wherein said device means further comprises:

first gate means disposed between and interconnecting said first operation register and said first operation decoder and responsive to said event signal for switching the contents of said second operation register to an input of said first operation decoder in response to said event signal thereby preventing the contents of said first operation register from reaching an input of said first operation decoder; and

second gate means disposed between and interconnecting said second operation register and said second operation decoder and responsive to said event signal for inhibiting the transfer of the contents of said second operation register to the second operation decoder in response to said event signal.

4. The device means of claim 3 further comprising:

further gate means connected to said second instruction cycle counter means and responsive to said event signal for freezing the counting of said machine cycles performed by said second instruction cycle counter means associated with the execution of said further instruction stored in said second operation register means in response to said event signal,

said count being provided by said second instruction cycle counter means being reinitiated and the execution of said further instruction continuing when said occurrence of event is terminated.

5. The device means of claim 4, further comprising:

circuit means connected to an output of said second operation register means and responsive to said further instructions and control information and connected to an input of said first gate means and said second gate means for controlling the operation of said first and second gate means.