Logic simulation machine

• US 4,656,580 A
• Filed: 06/11/1982
• Issued: 04/07/1987
• Est. Priority Date: 06/11/1982
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Graf, Matthew C., Hitchcock, Robert B. Sr.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/387,408
• Time in Patent Office: 1,761 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 703/19
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

An improved logic simulation machine in which non-unitary delays of logic functions being simulated are permitted and in which the delay time can be made different for low-to-high and high-to-low transitions. A plurality of basic processors are interconnected with a control processor through an inter-processor switch. The logic functions being simulated are divided among the various basic processors. The control processor provides primary input data and communicates the results computed by the basic processors with other ones of the basic processors as needed. All of the basic processors and the control processor operate in variable length work cycles. The length of a work cycle is determined by a minimum work space value among all of the logic functions to be simulated, that is, a minimum time to a next successive transition in a simulated output among all of the simulated logic functions. Further, the presence of glitches in the simulated output is detected. The detected glitches are suppressed if their duration is less than the delay time of the logic function being simulated for a particular transition it is predicted to undergo.

Claims

1. A method for simulating logic operations comprising the steps of:

simulating one or more time sequential logic functions in each of a plurality of basic processors operating in time unison, and determining a value of a simulated logic function output in each of said plurality of basic processors as a proposed output with a fixed constant delay for the logic function being simulated; and

delaying said proposed output from a final output for a delay time specific to said logic function being simulated.

2. The method of claim 1, wherein said delay time is further specific to whether said proposed output has changed from a high to a low logic level or from a low to a high logic level.

3. The method of either of claims 1 or 2, further comprising the steps of:

detecting the presence of a glitch in said proposed output of a duration less than the corresponding delay time of said logic function being simulated; and

inhibiting said glitch from said final output.

4. A method for simulating logic operations comprising the steps of:

simulating one or more time sequential logic functions in each of a plurality of basic processors, said logic functions in each of said basic processors being simulated in successive work cycles of logic operations;

determining, in each of said basic processors in each of said work cycles, a minimum work space value as a minimum time to a next successive logic operation among all logic functions simulated by said basic processor for each said work cycle;

determining a global minimum work space value among all said basic processors for each said work cycle as a minimum one of work space values among all of said basic processors; and

advancing each of said basic processors in time sequence in each of said work cycles by said global minimum work space value.

5. The method of claim 4, wherein said step of determining a minimum time to a next successive logic operation comprises:

calculating a time to a predicted simulated logic function output transition time in accordance with a stored delay time for each logic function to be simulated during each said work cycle; and

storing a minimum calculated time to a predicted simulated function output transition time among all of said logic functions simulated during each said work cycle.

6. The method of claim 5, wherein said step of calculating a time to a predicted simulated logic function output transition time comprises:

for an initial work cycle and for a first work cycle following a transition in said simulated function output for the function simulated, subtracting said global minimum work space value from said stored delay time for each said simulated logic function and storing the difference; and

repetitively for successive work cycles, for each said simulated logic function, and until a predicted transition occurs in said simulated logic function output, subtracting said minimum work space value from said difference and replacing said difference with a new difference thus calculated.

7. The method of claim 5, wherein said delay time is one of a first delay time value corresponding to low-to-high transitions and a second delay time value corresponding to high-to-low transitions of said simulated logic function output for each said simulated logic function.

8. The method of claim 7, further comprising the step of:

selecting one of said first and second delay time values in accordance with a state of a simulated logic function output in a present work cycle and in a work cycle immediately prior to a present work cycle where a transition of a simulated logic function output occurs.

9. The method of any one of claims 4-8 further comprising the steps of:

detecting presence of a glitch having a duration less than a corresponding delay time of a logic function being simulated; and

inhibiting said glitch in a simulated logic function output.

10. A method for simulating logic operations in successive work cycles in a plurality of basic processors, comprising the steps of:

I. in each of a plurality of basic processors and for each logic function simulated in each of said basic processors;

(a) determining a value LU IN of a simulated logic function output with a fixed constant minimum delay time;

(b) reading an old data value O_D (n), a saved data value S_D (n), a status bit value S_S (n) and a work space value WS(n) from a first signal value memory;

(c) reading at least one of a low-to-high delay time value LH and a high-to-low delay time value HL from an instruction memory;

(d) selecting one of said value WS(n), LH and HL in accordance with said values S_D (n) and S_S (n);

(e) if said value WS(n) is selected in step (d), subtracting a global minimum work space value GWS(n) therefrom and storing the difference value this calculated as a value WS(n+1), and if one of said values LH and HL is selected in step (d), storing the selected value as said value WS(n+1);

(f) performing a logic OR of individual bits of said value WS(n+1) to produce a signal WSO;

(g) performing logic operations;

space="preserve" listing-type="equation">SO=S.sub.S (n)+[(LU IN)+S.sub.D (n)],

space="preserve" listing-type="equation">GD=S.sub.S (n)"[(LU IN)+S.sub.D (n)],

and

space="preserve" listing-type="equation">S.sub.S (n+1)=WSO+SO+GD.

(h) selecting one of LU IN and O_D (n) as a final simulated logic function output in accordance with a state of S_S (n+1);

(i) storing said WS(n+1), S_S (n+1), S_D (n+1)=LU IN and O_D (n+1) in a second signal value memory for a next successive work cycle;

(j) repeating said steps (a) through (i) for each simulated logic function for each said work cycle alternating reading and storing in said first and second signal value memories;

II. for each said work cycle for each said basic processor, determining a minimum value of WS(n+1); and

III. for each said work cycle determining a global minimum work space value GWS(n+1) for a next successive work cycle as a minimum value of WS(n+1) among all of said basic processors.

11. The method of claim 10, wherein said step II comprises, in each of said basic processors:

initializing a register with a maximum value;

comparing each value of WS(n+1) for each logic function simulated with the content of said register; and

if said value of WS(n+1) is less than said content of said register, replacing said content of said register with WS(n+1), and otherwise retaining said content of said register.

12. The method of claim 11, wherein said step III comprises:

initializing a counter to a minimum count value;

incrementing said counter;

while incrementing said counter, comparing a count value of said counter with values remaining in each of said registers of each of said basic processors; and

when said count value first becomes equal to one of said values remaining in said registers, employing said count value than present as said global minimum work space value GWS(n+1).

13. A logic function simulator comprising a plurality of basic processors, a control processor, and an interprocessor switch interconnecting said basic processors and said control processor, each of said basic processors comprising:

means for storing delay times for each logic function simulated by that basic processor;

means operating in response to said storing means for determining a time to a next successive logic operation for each said simulated logic function in accordance with a corresponding delay time;

means operating in response to said time determining means for determining a minimum work space value as a minimum time to a next successive logic operation among all said simulated logic functions; and

means for advancing said basic processor in time sequence by a global minimum work space value, said global minimum work space value being a minimum one of minimum work space values among all said basic processors.

14. The logic function simulator of claim 13, wherein said means for determining a time to a next successive logic operation for each said simulated logic function comprises means for subtracting said global minimum work space value from a delay time for each said simulated logic function.

15. The logic functions simulator of claim 14, wherein said subtracting means subtracts said global minimum work space value from said delay time for said simulated logic function for an initial cycle related to a predetermined logic operation and thereafter for successive cycles subtracts said global minimum work space value from a difference thus calculated and replaces said difference with a new difference determined by subtracting said global minimum work space value from the previous difference.

16. The logic function simulator of claim 15, further comprising means for calculating a new value of said global minimum work space value for each said cycle.

17. The logic function simulator of any one of claims 13-16 further comprising:

means for detecting the presence of a glitch in a simulated output for each said simulated logic function of a duration less than the corresponding delay time of said simulated logic function; and

means for inhibiting said glitch.

18. A logic function simulator comprising a plurality of basic processors, a control processor, and an interprocessor switch interconnecting said basic processors and said control processor, said basic processors and said control processor comprising means for simultaneously advancing said basic processors and said control processor through logic operations to be simulated in each work cycle, at a time interval equivalent to a minimum time to a next successive logic operation, among all said basic processors, said minimum time being determined in each said work cycle.

19. The logic function simulator of claim 18, wherein said advancing means comprises means in each of said basic processors for storing delay times for each logic function being simulated, said delay times including delay times for each of a low-to-high and high-to-low transition of each simulated output of each simulated logic function;

means for selecting one of said delay times corresponding to a low-to-high transition or a high-to-low transition in accordance with a type of transition predicted for each said simulated logic function; and

means for accumulatively subtracting a global minimum work space value from the selected delay time for each said simulated logic function, said global minimum work space value being a minimum work space value among all of said basic processors.

20. The logic function simulator of either one of claims 18 or 19 further comprising:

means for detecting the presence of a glitch in each simulated output of each said simulated logic function having a duration less than a corresponding delay time for a corresponding simulated logic function; and

means for inhibiting said glitch.

21. A logic function simulator comprising:

I. a plurality of basic processors, each of said processors comprising;

(a) means for determining a value of a simulated logic function output as a proposed output LU IN with a fixed constant delay for the logic function being simulated;

(b) first and second signal value memories;

(c) means for storing data received from said first and second signal value memories, said data received from said signal value memories including an old data value O_D (n), a saved data value S_D (n), a status bit value S_S (n) and a work space value WS(n);

(d) an instruction memory for storing a low-to-high delay time value LH and a high-to-low delay time value HL for each logic function simulated by the basic processor;

(e) multiplexer means for selecting one of WS(n), LH and HL in accordance with S_S (n) and S_D (n);

(f) subtractor means for subtracting a minimum work space value from WS(n) to obtain a value WS(n+1) if said WS(n) is selected and passing the selected of said LH and HL if one of said LH and HL is selected;

(g) logic circuit means operating in response to an output of said subtracting means, said signals LU IN, O_D (n), S_D (n) and S_S (n) for determining a next successive value S_S (n+1) of S_S (n) indicative of whether or not a change in said LU IN has occurred but is not yet to be propagated;

(h) means for selecting as an output O_D (n+1) one of LU IN and O_D (n+1) in accordance with an output of said logic circuit means; and

(i) switch means for loading into a selected one of said first and second signal value memories said S_S (n+1), LU IN=S_D (n+1), O_D (n+1) and WS(n+1) to become O_D (n), S_S (n) and WS(n), respectively, for a next successive work cycle for a corresponding logic function;

II. a control processor for providing primary signal inputs to said basic processors; and

III. an inter-processor switch for interconnecting said basic processor and said control processor.