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Logic simulation machine

  • US 4,656,580 A
  • Filed: 06/11/1982
  • Issued: 04/07/1987
  • Est. Priority Date: 06/11/1982
  • Status: Expired due to Fees
First Claim
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1. A method for simulating logic operations comprising the steps of:

  • simulating one or more time sequential logic functions in each of a plurality of basic processors operating in time unison, and determining a value of a simulated logic function output in each of said plurality of basic processors as a proposed output with a fixed constant delay for the logic function being simulated; and

    delaying said proposed output from a final output for a delay time specific to said logic function being simulated.

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