Very large scale integrated circuit subdivided into isochronous regions, method for the machine-aided design of such a circuit, and method for the machine-aided testing of such a circuit

• US 4,656,592 A
• Filed: 10/10/1984
• Issued: 04/07/1987
• Est. Priority Date: 10/14/1983
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: van der Poel, Arie A., Duin, Peter B., Spaanenburg, Lambertus, Woudsma, Roberto
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Juffernbruch, Daniel W.
• Application Number:
  US06/659,395
• Time in Patent Office: 909 Days
• Field of Search: 364/490, 364/491, 364/579, 364/580, 364/200 MS File, 364/900 MS File, 371/16, 307/303, 357/45
• US Class Current: 716/125
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A very large scale integrated circuit comprises a number of function blocks which are synchronized by relevant clock signals. Each function block forms an isochronous region so that the delay times of the signals within the relevant function block can be negligibly small with respect to the gate delay times. Each function block is paired with at least one other function block in that the pair is connected by an information connection and by at least two synchronization handshake lines for transporting synchronization signals dispatched by each function block of the pair to the other function block of the pair so that an asynchronous information transport is obtained. One or more of the function blocks comprises an information connection to the environment. As a result of this set-up, the circuit can also be tested and designed per function block.

Claims

1. A very large scale integrated circuit comprising a plurality of function cells which are connected to one another and to the environment by means of information connections, wherein said function cells are grouped in a number of m≧

3 function blocks, the integrated circuit which is formed on a single chip being subdivided into m isochronous regions, each of which comprises one function block, each isochronous region comprising for each information connection a communication cell between a function cell which is situated within the isochronous region and any function cell which is situated outside said isochronous region, said communication cell being connected in the relevant information connection so that any information connection between two function cells which are situated in different isochronous regions always comprises a series connection of two communication cells, two communications cells thus paired being interconnected by an information connection and at least two synchronization connections for by means of bidirectional handshake signals under local control realizing as asynchronous information transport between said paired communication cells, and therefore between the associated isochronous regions, each information connection from any function cell to the environment comprising a further communication cell for the exchange of information and synchronization signals with the environment, the function cells within a function block forming a coherent first network while the function blocks within the integrated circuit form a coherent second network.

2. An integrated circuit as claimed in claim 1, wherein at least two function blocks which are paired by way of intermediate communication cells both comprise processing function cells.

3. An integrated circuit as claimed in claim 1 or claim 2, wherein the connection between a first function block and a second function block comprises a first set of information lines, the connection between the first function block and a third information block comprises a second set of information lines, and said first and second set are different.

4. An integrated circuit as claimed in claim 3, wherein the numbers of information lines in said first and said second sets are different.

5. An integrated circuit as claimed in claim 4 wherein the number of data lines in said first and said second sets are different.

6. An integrated circuit as claimed in claims 1 or 2, wherein the information connection between an isochronous region and further function blocks comprises a register bank which can be selectively coupled to said further function blocks under the control of relevant control blocks.

7. An integrated circuit as claimed in claim 1, wherein at least three function cells which are situated in a corresponding number of mutually paired isochronous regions are connected by means of communication cells with intermediate information lines each of which is unidirectionally conductive in a direction from the directly preceding isochronous region to the directly subsequent isochronous region.

8. An integrated circuit as claimed in claims 1 or 2 comprising a microprocessor having at least a function block which performs arithmetic and logic functions, a memory function block and an input/output function block which comprises an information connection to the environment.

9. An integrated circuit as claimed in claim 1 or 2 comprising at least one isochronous region including means for supplying a test pattern or result pattern received from another isochronous region bit by bit to a third isochronous region when the integrated circuit is in a test state.

10. A method of testing an integrated circuit as claimed in claim 9 comprising the steps of:

(a) setting the integrated circuit to a test state;

(b) presenting a test pattern to a function block in order to form a result pattern from said test pattern while excluding information signals which can be received from other function blocks;

(c) outputting said result pattern of said function block for bit-by-bit presentation to a test circuit;

(d) repeating, if necessary, the steps (b) and (c) while using other test patterns;

(e) verifying the result patterns for correctness until a reliability limit is reached or an error is detected;

(f) repeating, if necessary, the steps (b) to (e) for further function blocks to be tested;

(g) approving the complete integrated circuit on the basis of the reliability limits reached or rejecting the integrated circuit on the basis of the errors detected;

(h) setting the integrated circuit to a ready state in the case of approval.

11. An integrated circuit as claimed in claims 1 or 2, comprising a function block to be tested which is connected to the connection to the environment via a group of further function blocks wherein said group forms a chain of function blocks for supplying test patterns to the function block to be tested or for outputting result patterns from the function block to be tested and in which each isochronous region whose function block is included in the chain comprises communication cells which are included in the chain, each of said communication cells having multiplexed first and second states, said first state for activating the associated function block and said second state for supplying a test pattern or result pattern received from a second isochronous region bit-by-bit to a third isochronous region.

12. An integrated circuit as claimed in claims 1 or 2, wherein at least one isochronous region comprises information connection means for communicating, in a test state of the integrated circuit, a result pattern of a test to a test circuit, said isochronous region otherwise comprising exclusively information connections to other isochronous regions.

13. An integrated circuit as claimed in claim 12 wherein said information connection means comprise a conductor which is common to several isochronous regions for outputting a result pattern.

14. An integrated circuit as claimed in claims 1 or 2, wherein at least one isochronous region comprises information connection means for communicating, in a test state of the integrated circuit, a test pattern and a result pattern produced by said test pattern to a test circuit, said isochronous region otherwise comprising exclusively information connections to other isochronous regions.

15. A method of designing a very large scale integrated circuit as claimed in claim 1 by means of a library of shape elements which define the behavior model of the associated function cells comprising the steps of:

(a) describing the group of functions to be performed by the circuit with respect to the environment as a first list of functions which is to be displayed on a display element;

(b) dividing said group into separate function blocks for display on a display element in the form of a second list;

(c) defining a group of m≧

3 isochronous regions, each of which consists of one function block, and also defining the interactions between different function cells in different function blocks in order to add a communication cell to each function cell within a function block having an information connection to a function cell which is situated outside the relevant function block, so that each information connection between two function cells which are situated in different isochronous regions comprises a series connection of a pair of communication cells, a communication cell comprising a shape element as a connection for an information connection and a synchronization handshake element with two synchronization handshake lines;

(d) positioning the function blocks, communication cells, connecting information connections and synchronization handshake connections;

(e) fetching the shape elements defined per function cell from the library.

16. A very large scale integrated circuit comprising a plurality of function cells for together executing a first set of digital data processing functions, said circuit being distributed over a plurality of at least three isochronous regions, in each of which any internal operation is independent of any signal delay time variation therein;

each isochronous region comprising a second set of interconnected function cells together constituting a single function block;

wherein a particular first function cell in a first isochronous region is connected by a first information connection with a particular second function cell in a second isochronous region, and a third function cell in said second isochronous region is connected by a second information connection with a particular fourth function cell in a third isochronous region, said first information connection having a first communication cell within said first isochronous region and a second communiation cell within a said second isochronous region, said second information connection having a third communication cell within said second isochronous region, and a fourth communication cell within said third isochronous region, wherein said first and second communication cells are interconnected by at least two handshake connections for bidirectionally transporting handshake signals for realizing under local control an asynchronous information transport between the associated communication cells, and wherein said third and fourth communication cells are interconnected by at least two further handshake connections for bidirectionally transporting further handshake signals for realizing under local control a further asynchronous information transport between the associated communication cell, and wherein at least one fifth function cell is provided with a fifth communication cell attached thereto, said fifth communication cell being provided with synchronizing means and at least one external handshake connection for realizing an exchange of synchronization and information signals with an external circuit connectable to said fifth communication cell.