Multi-function load controller for carrier load control subsystem

• US 4,656,593 A
• Filed: 05/20/1985
• Issued: 04/07/1987
• Est. Priority Date: 05/20/1985
• Status: Expired due to Term

• Current Assignee: Westinghouse Electric Company LLC (Brookfield Asset Management Incorporated)
• Original Assignee: Westinghouse Electric Company LLC (Brookfield Asset Management Incorporated)
• Inventors: Stamatien, James A., Gleba, James S., Fortune, Gregory B.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US06/736,171
• Time in Patent Office: 687 Days
• Field of Search: 371/37, 364/492, 364/493, 340/825.02, 340/825.03, 340/825.06, 340/310, 340/310 A, 307/38, 307/40
• US Class Current: 700/295
• CPC Class Codes: H02J 13/00009 using pulsed signals
• CPC Class Codes: H02J 2310/54 according to a pre-established time schedule
• CPC Class Codes: H02J 2310/60 Limiting power consumption in the network or in one section of the network, e.g. load shedding or peak shaving
• CPC Class Codes: H02J 2310/66 one of the loads acting as master and the other or others acting as slaves
• CPC Class Codes: H02J 3/14 by switching loads on to, or off from, network, e.g. progressively balanced loading
• CPC Class Codes: H04Q 9/14 Calling by using pulses

Abstract

A low cost, software based, 4 bit microprocessor is pin configurable to function either as a central controller in a communication and control network or as a slave load control unit in said network. The microprocessor when configured as a slave unit can also function as a customer service unit to inform a customer of existing utility rates and permit him to override an existing load management schedule if he so desires.

Claims

1. In a bi-directional communication and control system,

a multipurpose two-way communication device coupled to a communication network line for receiving digital messages from and transmitting digital messages to said network, said device being operable in a first mode in which said device includes means for receiving and decoding a digital signal message from said network line and means responsive to the decoded message for executing a control function in accordance with an instruction contained in the decoded message, said device also being operable in a second mode in which said device includes means for receiving and storing a digital message from a master controller which includes an address portion and a function portion, means for generating a series of error checking bits the logic value of which is determined by the bits of said stored digital message, and means for developing a transmission output signal which includes at least the function portion of said stored digital message and said error checking bits.

2. A bi-directional communication and control system as set forth in claim 1, which includes means for generating a carrier signal of predetermined frequency, means for modulating said output signal on said carrier signal, and means for coupling said modulated carrier signal to said communication network line.

3. The control system of claim 1, wherein said device includes means operable in said second mode for changing the address portion of said stored digital message and including the changed address in said output signal.

4. The control system of claim 1, wherein said series of error checking bits comprise a plural bit BCH error checking code.

5. The control system of claim 1, wherein said received digital message from said network line includes a series of error checking bits and said device includes means operable in said first mode for calculating an error checking code based on the logic value of the bits of said received message other than said series of error checking bits, and means for comparing said calculated error checking code with said series of error checking bits of said received message.

6. The control system of claim 5, wherein said received message includes an address portion, and means controlled by said error checking bits comparing means for comparing said address portion of said received message with an address assigned to said device.

7. The control system of claim 1, wherein said device includes means operable in said second mode for altering the address portion of said stored digital message in accordance with an address assigned to said device and substituting said altered address portion in said output signal in place of said address portion of said stored digital message.

8. The control system of claim 1, wherein said received digital message from said network line includes a series of error checking bits and said device includes means operable in said first mode for calculating an error checking code based on the logic value of the bits of said received message other than said series of error checking bits, and means for producing a control signal when the respective bits of said calculated error checking code are the same as said series of error checking bits of said message received from said network line.

9. The control system of claim 8, wherein said message received from said network line includes an address portion, and means operative in response to said control signal for comparing said address portion of said received message with an address assigned to said device and developing a second control signal when said addresses are equal.

10. The control system of claim 9, wherein said device includes means operative in said first mode and responsive to said second control signal for executing said control function.

11. A multipurpose two-way communication device coupled to a communication network line for receiving digital messages from and transmitting digital messages to said network, said device being operable in a slave mode in which said device includes means for receiving and storing a digital message from said network line which includes a function portion and means responsive to the function portion of said stored message for executing a control function in accordance therewith, said device also being operable in a master mode in which said device includes means for receiving and storing a digital message from a master controller which includes a function portion, and means for developing a digital transmission output signal for said network line which includes two start bits and said function portion of said stored master message.

12. A device as claimed in claim 11, wherein said master message also includes an address portion, and means operative in said master mode of said device for altering said stored address portion of said master message and including said altered address in said transmission output signal.

13. A bidirectional communication and control system which includes a device as set forth in claim 11, means for generating a carrier signal of predetermined frequency, means for modulating said transmission output signal on said carrier signal, and means for coupling said modulated carrier signal to said communication network line.

14. A system as set forth in claim 13, wherein said first start bit of said modulated carrier signal comprises the presence of carrier on said network line and said second start bit comprises the absence of carrier on said line.

15. A system as set forth in claim 13, wherein each bit of said modulated carrier signal other than said start bits comprise a first carrier-on portion of predetermined duration and a second data portion in which carrier is present or absent depending upon the logic value of said bit.

16. A system as set forth in claim 13, which includes means for receiving a modulated carrier signal reply message from said communication network line, said receiving means including a phase lock loop circuit including an oscillator having a center frequency corresponding to the unmodulated carrier frequency of said reply message.

17. A system as set forth in claim 16, wherein said phase lock loop oscillator is also employed as said carrier signal generating means when said modulated carrier signal is coupled to said communication network line.

18. A system as set forth in claim 11, wherein said device includes a control input terminal, means operative in response to a first electrical condition of said control terminal for establishing said first mode of operation of said device, and means operative in response to a different electrical condition of said control terminal for establishing said second mode of operation of said device.

19. A system as set forth in claim 18, wherein said device includes a microprocessor having first program means for establishing said first mode of operation and second program means for establishing said second mode of operation, and means operative in response to the electrical condition of said control terminal for selecting one of said first and second program means.

20. A device as set forth in claim 11, wherein said device includes a control input terminal, means operative in response to a first electrical condition of said control terminal for establishing said slave mode of operation of said device, and mean operative in response to a different electrical condition of said control terminal for establishing said master mode of operation of said device.

21. A device as set forth in claim 20, wherein said device includes a microprocessor having first program means for establishing said slave mode of operation and second program means for establishing said master mode of operation, and means operative in response to the electrical condition of said control terminal for selecting one of said first and second program means.

22. In a communication and control system, the combination of, a common network line, transmitting means for placing on said network line an on-off keyed carrier signal message having a plurality of data bits each of which comprises a first carrier-on portion of predetermined duration and a succeeding data portion in which carrier is present or absent depending upon the logic value of said bit, and receiving means coupled to said network line for detecting said message, said receiving means including means for periodically sampling each bit of said message over a time interval which starts during the carrier-on portion of one bit and ends during the carrier-on portion of the next bit, and means controlled by said sampling means for assigning a first logic value to the sampled bit if all of the samples during a given interval correspond to the presence of carrier and a second logic value to the sampled bit if any one of the samples during said given interval corresponds to the absence of carrier.

23. The combination of claim 22, wherein the presence of carrier in said data portion of each bit of said message placed on said network line denotes a logic value of "0".

24. The combination of claim 22, wherein said receiving means includes a microprocessor, means for coupling said network line to a data input of said microprocessor, said sampling means comprising a program for reading said data input, the period of said sampling means being determined by the run time of said program.

25. The combination of claim 22 wherein said receiving means includes microprocessor means coupled to said network line and programmed to read the received carrier signal message a number of times during each bit thereof, the number of times each bit is read being determined by the loop running time of said program.

26. The combination of claim 22, which includes a phase lock loop circuit coupled to said network line, and said sampling means comprising microprocessor means having a data input connected to the output of said phase lock loop circuit.

27. The combination of claim 26, wherein said microprocessor means including a program for repeatedly reading the output of said phase lock loop circuit, the number of times each bit is read being determined by the run time of said program.

28. The combination of claim 22, wherein said message placed on said network line includes two start bits each having a duration equal to a data bit thereof.

29. The combination of claim 23, wherein said message placed on said network line includes two start bits each having a duration equal to a data bit thereof, said first start bit having a logic value of "0".

30. The combination of claim 29, wherein said second start bit has a first portion having a logic value of "0" and a second portion having a logic value of "1".

31. The combination of claim 30, wherein said first and second portions of said second start bit are of equal duration.

32. The combination of claim 30, wherein said sampling means is synchronized with the "0" to "1" transition of said second start bit.