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Semiconductor memory device having redundancy means

  • US 4,656,610 A
  • Filed: 01/23/1984
  • Issued: 04/07/1987
  • Est. Priority Date: 01/21/1983
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory device comprising:

  • first and second memory arrays, each having a plurality of memory cells formed along rows and columns;

    first selection means for selecting at least one memory cell column designated by first address signals, from said first and second memory arrays upon receiving said first address signals;

    second selection means for selecting memory cell rows from said first and second memory arrays;

    a first common data line for receiving data of a memory cell which has been selected from said first memory array by said first and second selection means;

    a second common data line for receiving data of a memory cell which has been selected from said second memory array by said first and second selection means;

    a first spare memory comprising at least one memory cell column formed with a plurality of memory cells, and providing data of a memory cell designated by said second selection means from said first spare memory to said first common data line in response to a first selection signal;

    a second spare memory comprising at least one memory cell column formed with a plurality of memory cells, and providing data of a memory cell designated by said second selection means from said second spare memory to said second common data line in response to a second selection signal;

    first amplifier means coupled to said first common data line, and operating in response to the selection of a memory cell from said first memory array so that data of the memory cell selected is amplified by said first amplifier means;

    second amplifier means coupled to said second common data line, and operating in response to the selection of a memory cell from said second memory array so that data of the memory cell selected is amplified by said second amplifier means;

    first redundancy means receiving second address signals including at least said first address signals, and for generating a first control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays;

    second redundancy means receiving said second address signals, and for generating a second control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays; and

    control means responsive to said first and second control signals, for generating one of said first and second selection signals, for inhibiting the selection of a memory cell column from one of said first and second memory arrays, and for operating either one of said first and second amplifier means so that data of a memory cell in either one of said first and second spare memories instead of the defective memory cell column in either one of said first and second memory arrays is amplified by the one of the first and second amplifier means which is operated.

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