Semiconductor memory device having redundancy means
First Claim
1. A semiconductor memory device comprising:
- first and second memory arrays, each having a plurality of memory cells formed along rows and columns;
first selection means for selecting at least one memory cell column designated by first address signals, from said first and second memory arrays upon receiving said first address signals;
second selection means for selecting memory cell rows from said first and second memory arrays;
a first common data line for receiving data of a memory cell which has been selected from said first memory array by said first and second selection means;
a second common data line for receiving data of a memory cell which has been selected from said second memory array by said first and second selection means;
a first spare memory comprising at least one memory cell column formed with a plurality of memory cells, and providing data of a memory cell designated by said second selection means from said first spare memory to said first common data line in response to a first selection signal;
a second spare memory comprising at least one memory cell column formed with a plurality of memory cells, and providing data of a memory cell designated by said second selection means from said second spare memory to said second common data line in response to a second selection signal;
first amplifier means coupled to said first common data line, and operating in response to the selection of a memory cell from said first memory array so that data of the memory cell selected is amplified by said first amplifier means;
second amplifier means coupled to said second common data line, and operating in response to the selection of a memory cell from said second memory array so that data of the memory cell selected is amplified by said second amplifier means;
first redundancy means receiving second address signals including at least said first address signals, and for generating a first control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays;
second redundancy means receiving said second address signals, and for generating a second control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays; and
control means responsive to said first and second control signals, for generating one of said first and second selection signals, for inhibiting the selection of a memory cell column from one of said first and second memory arrays, and for operating either one of said first and second amplifier means so that data of a memory cell in either one of said first and second spare memories instead of the defective memory cell column in either one of said first and second memory arrays is amplified by the one of the first and second amplifier means which is operated.
1 Assignment
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Accused Products
Abstract
The semiconductor memory device includes at least two memory arrays, a first selection circuit which selects a memory cell from either one of the memory arrays in accordance with address signals, preferably two spare memory arrays and a second selection circuit which selects a memory cell from either one of the spare memory arrays. If a defective memory cell or cells are contained in one of the two memory arrays, the second selection circuit an select a spare memory cell or cells from any of the two spare memory arrays in place of the defective memory cell or cells. Thus, the spare memory arrays can be used effectively. Two sets of main amplifiers are also disposed and only one of them, which receives the data from the memory cell selected from the memory arrays or spare memory arrays, is operated. Thus, lower power consumption can be realized.
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Citations
22 Claims
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1. A semiconductor memory device comprising:
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first and second memory arrays, each having a plurality of memory cells formed along rows and columns; first selection means for selecting at least one memory cell column designated by first address signals, from said first and second memory arrays upon receiving said first address signals; second selection means for selecting memory cell rows from said first and second memory arrays; a first common data line for receiving data of a memory cell which has been selected from said first memory array by said first and second selection means; a second common data line for receiving data of a memory cell which has been selected from said second memory array by said first and second selection means; a first spare memory comprising at least one memory cell column formed with a plurality of memory cells, and providing data of a memory cell designated by said second selection means from said first spare memory to said first common data line in response to a first selection signal; a second spare memory comprising at least one memory cell column formed with a plurality of memory cells, and providing data of a memory cell designated by said second selection means from said second spare memory to said second common data line in response to a second selection signal; first amplifier means coupled to said first common data line, and operating in response to the selection of a memory cell from said first memory array so that data of the memory cell selected is amplified by said first amplifier means; second amplifier means coupled to said second common data line, and operating in response to the selection of a memory cell from said second memory array so that data of the memory cell selected is amplified by said second amplifier means; first redundancy means receiving second address signals including at least said first address signals, and for generating a first control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays; second redundancy means receiving said second address signals, and for generating a second control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays; and control means responsive to said first and second control signals, for generating one of said first and second selection signals, for inhibiting the selection of a memory cell column from one of said first and second memory arrays, and for operating either one of said first and second amplifier means so that data of a memory cell in either one of said first and second spare memories instead of the defective memory cell column in either one of said first and second memory arrays is amplified by the one of the first and second amplifier means which is operated. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 17, 18)
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9. A semiconductor memory device comprising:
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a first memory array having a plurality of memory cells having control and input-output terminals and arranged in a matrix; a second memory array having a plurality of memory cells having control and input-output terminals and arranged in a matrix; first selection means for selecting memory cell rows from said first and second memory arrays; second selection means receiving first address signals, and for selecting memory cell columns designated by said first address signals from said first and second memory arrays; a plurality of first common data lines for receiving data of memory cells selected by said first and second selection means from said first memory array; a plurality of second common data lines for receiving data of memory cells selected by said first and second selection means from said second memory array; a first spare memory array including a plurality of memory cells arranged in a matrix, wherein a spare memory cell row is selected by said first selection means, and data of the memory cells selected are transmitted to said first common data lines in response to a first selection signal; a second spare memory array including a plurality of memory cells arranged in a matrix, wherein a spare memory cell row is selected by said first selection means, and data of the memory cells selected are transmitted to said second common data lines in response to a second selection signal; a plurality of first amplifier means coupled to respective ones of said first common data lines, and operating in response to the selection of memory cells from said first memory array so that data of the memory cells selected are amplified by said first amplifier means; a plurality of second amplifier means coupled to respective ones of said second common data lines, and operating in response to the selection of memory cells from said second memory array so that data of the memory cells selected are amplified by said second amplifier means; first redundancy means receiving second address signals including at least said first address signals, and for generating a first control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays; second redundancy means receiving said second address signals, and for generating a second control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays; control means responsive to said first and second control signals, for generating one of said first and second selection signals, for inhibiting the selection of memory cell columns from one of said first and second memory arrays, and for operating ones of said first and second amplifier means so that data of memory cells in either one of said first and second spare memory arrays instead of memory cells in either one of said first and second memory arrays are amplified by the one of the first and second amplifier means which is operated. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 19)
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20. A semiconductor memory device comprising:
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first and second memory arrays, each having a plurality of memory cells formed along rows and columns; first selection means for selecting at least one memory cell column indicated by first address signals from said first and second memory arrays; a first common data line for receiving data of a memory cell in the memory cell column selected by said first selection means from said first memory array; a second common data line for receiving data of a memory cell in the memory cell column selected by said first selection means from said second memory array; a spare memory comprising at least one memory cell column formed with a plurality of memory cells, and providing data of a memory cell in said spare memory to said first common data line in response to a predetermined selection signal; first amplifier means coupled to said first common data line, and operating in response to the selection of a memory cell from said first memory array so that data on said first common data line is amplified by said first amplifier means; second amplifier means coupled to said second common data line, and operating in response to the selection of a memory cell from said second memory array so that data on said second common data line is amplified by said second amplifier means; redundancy means receiving second address signals comprising at least said first address signals, and for generating a control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays; and control means responsive to said control signal, for generating said predetermined selection signal, for inhibiting the selection of a memory cell column from said first memory array, and for generating a timing signal for operating said first amplifier means so that data of a memory cell in said spare memory instead of the defective memory cell column in either one of said first and second memory arrays is amplified by said first amplifier means. - View Dependent Claims (21, 22)
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Specification