Semiconductor memory device having redundancy means

• US 4,656,610 A
• Filed: 01/23/1984
• Issued: 04/07/1987
• Est. Priority Date: 01/21/1983
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd., Hitachi Microcomputer Engineering Limited (Hitachi, Ltd.)
• Original Assignee: Hitachi, Ltd.
• Inventors: Oishi, Kanji, Yoshida, Masahiro
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/573,139
• Time in Patent Office: 1,170 Days
• Field of Search: 365/200, 365/189, 371/10, 371/21
• US Class Current: 365/189.07
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 29/83 with reduced power consumption

Abstract

The semiconductor memory device includes at least two memory arrays, a first selection circuit which selects a memory cell from either one of the memory arrays in accordance with address signals, preferably two spare memory arrays and a second selection circuit which selects a memory cell from either one of the spare memory arrays. If a defective memory cell or cells are contained in one of the two memory arrays, the second selection circuit an select a spare memory cell or cells from any of the two spare memory arrays in place of the defective memory cell or cells. Thus, the spare memory arrays can be used effectively. Two sets of main amplifiers are also disposed and only one of them, which receives the data from the memory cell selected from the memory arrays or spare memory arrays, is operated. Thus, lower power consumption can be realized.

Claims

1. A semiconductor memory device comprising:

first and second memory arrays, each having a plurality of memory cells formed along rows and columns;

first selection means for selecting at least one memory cell column designated by first address signals, from said first and second memory arrays upon receiving said first address signals;

second selection means for selecting memory cell rows from said first and second memory arrays;

a first common data line for receiving data of a memory cell which has been selected from said first memory array by said first and second selection means;

a second common data line for receiving data of a memory cell which has been selected from said second memory array by said first and second selection means;

a first spare memory comprising at least one memory cell column formed with a plurality of memory cells, and providing data of a memory cell designated by said second selection means from said first spare memory to said first common data line in response to a first selection signal;

a second spare memory comprising at least one memory cell column formed with a plurality of memory cells, and providing data of a memory cell designated by said second selection means from said second spare memory to said second common data line in response to a second selection signal;

first amplifier means coupled to said first common data line, and operating in response to the selection of a memory cell from said first memory array so that data of the memory cell selected is amplified by said first amplifier means;

second amplifier means coupled to said second common data line, and operating in response to the selection of a memory cell from said second memory array so that data of the memory cell selected is amplified by said second amplifier means;

first redundancy means receiving second address signals including at least said first address signals, and for generating a first control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays;

second redundancy means receiving said second address signals, and for generating a second control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays; and

control means responsive to said first and second control signals, for generating one of said first and second selection signals, for inhibiting the selection of a memory cell column from one of said first and second memory arrays, and for operating either one of said first and second amplifier means so that data of a memory cell in either one of said first and second spare memories instead of the defective memory cell column in either one of said first and second memory arrays is amplified by the one of the first and second amplifier means which is operated.

2. The semiconductor memory device as defined in claim 1, wherein said first redundancy means includes a memory circuit for storing address signals designating a defective memory column and a comparison circuit for comparing said address signals stored in said memory circuit with said second address signals, so that said first control signal is generated when said second address signals are the address signals which select said defective memory cell column, and wherein said second redundancy means includes a memory circuit for storing address signals designating defective memory cell columns and a comparison circuit for comparing said address signal stored in said memory circuit with said second address signals, so that said second control signal is generated when said second address signals are the address signals which select a defective memory cell column.

3. The semiconductor memory device as defined in claim 2, wherein said control means further receives a part of said second address signals and produces said first selection signal for selecting a memory cell from said first spare memory or said second selection signal for selecting a memory cell from said second spare memory.

4. The semiconductor memory device as defined in claim 3, wherein said part of said second address signals is an address signal designating the selection of a memory cell column from either one of said first and second memory arrays.

5. The semiconductor memory device as defined in claim 4, which further includes a timing circuit for generating a timing signal, and wherein said control means comprises a logic circuit coupled to receive said first and second control signals and said part of said second address signals and to produce a change-over control signal, and a multiplexor receiving said timing signal generated by said timing circuit and said change-over control signal generated by said logic circuit and producing said timing signal as said first or second selection signal in accordance with said change-over control signal.

6. The semiconductor memory device as defined in claim 2, wherein said first selection circuit includes a first address decoder which selects a memory cell column from said first memory array and whose operation is controlled by said control means, and a second address decoder which selects a memory cell column from said second memory array and whose operation is controlled by said control means.

7. The semiconductor memory device as defined in claim 2, wherein each of said memory cell rows comprises a word line and a plurality of memory cells whose control terminals are connected to said word line, each of said memory cell columns comprises a data line pair and a plurality of memory cells, each of said memory cells having an output terminal connected to one of the data lines of said data line pair, and each of said first and second common data lines comprises a common data line pair.

8. The semiconductor memory device as defined in claim 7, further comprising a first column switch circuit receiving the selection signal produced from said first selection means and connecting said first common data line pair to a data line pair in said memory cell column in said first memory array selected by said selection signal produced by said first selection means, a second column switch circuit receiving the selection signal produced from said first selection means and connecting said second common data line pair to a data line pair of said memory cell column in said second memory array designated by said selection signal produced from said first selection means, a first spare column switch circuit receiving said first selection signal produced from said control means and connecting said first common data line pair to a data line pair of a memory cell column in said first spare memory in response to said first selection signal, and a second spare column switch circuit receiving said second selection signal produced from said control means and connecting said second common data line pair to a data line pair of a memory cell column in said second spare memory in response to said second selection signal.

17. The semiconductor memory device as defined in claim 8, wherein said first selection means comprises a first address decoder circuit for providing said selection signal to be supplied to said first column switch circuit, and a second address decoder circuit for providing said selection signal to be supplied to said second column switch circuit.

18. The semiconductor memory device as defined in claim 8, further comprising a timing signal generating circuit, and wherein said control means comprises means receiving a timing signal produced from said timing signal generating circuit and for generating a first timing signal for controlling the operation of said first amplifier means and a second timing signal for controlling the operation of said second amplifier means.

9. A semiconductor memory device comprising:

a first memory array having a plurality of memory cells having control and input-output terminals and arranged in a matrix;

a second memory array having a plurality of memory cells having control and input-output terminals and arranged in a matrix;

first selection means for selecting memory cell rows from said first and second memory arrays;

second selection means receiving first address signals, and for selecting memory cell columns designated by said first address signals from said first and second memory arrays;

a plurality of first common data lines for receiving data of memory cells selected by said first and second selection means from said first memory array;

a plurality of second common data lines for receiving data of memory cells selected by said first and second selection means from said second memory array;

a first spare memory array including a plurality of memory cells arranged in a matrix, wherein a spare memory cell row is selected by said first selection means, and data of the memory cells selected are transmitted to said first common data lines in response to a first selection signal;

a second spare memory array including a plurality of memory cells arranged in a matrix, wherein a spare memory cell row is selected by said first selection means, and data of the memory cells selected are transmitted to said second common data lines in response to a second selection signal;

a plurality of first amplifier means coupled to respective ones of said first common data lines, and operating in response to the selection of memory cells from said first memory array so that data of the memory cells selected are amplified by said first amplifier means;

a plurality of second amplifier means coupled to respective ones of said second common data lines, and operating in response to the selection of memory cells from said second memory array so that data of the memory cells selected are amplified by said second amplifier means;

first redundancy means receiving second address signals including at least said first address signals, and for generating a first control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays;

second redundancy means receiving said second address signals, and for generating a second control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays;

control means responsive to said first and second control signals, for generating one of said first and second selection signals, for inhibiting the selection of memory cell columns from one of said first and second memory arrays, and for operating ones of said first and second amplifier means so that data of memory cells in either one of said first and second spare memory arrays instead of memory cells in either one of said first and second memory arrays are amplified by the one of the first and second amplifier means which is operated.

10. The semiconductor memory device as defined in claim 9, wherein said first redundancy means includes a memory circuit for storing address signals designating the defective memory cell column and a comparison circuit comparing said address signals stored in said memory circuit with said second address signals, whereby said first redundancy means produces said first control signal when said address signals stored in said memory circuit and said second address signals coincide with each other, and wherein said second redundancy means includes a memory circuit for storing address signals designating the defective memory cell column and a comparison circuit comparing said address signals stored in said memory circuit with said second address signals, whereby said second redundancy means produces said second control signal when said address signals stored in said memory circuit and said second address signals coincide with each other.

11. The semiconductor memory device as defined in claim 9, wherein said control means comprises a logic circuit receiving said first and second control signals and a part of said second address signals, first means receiving the change-over control signal produced from said logic circuit and for generating one of said first and second selection signals, and second means receiving said change-over control signal and for generating a first timing signal for controlling the operation of said first amplifier means and a second timing signal for controlling the operation of said second amplifier means.

12. The semiconductor memory device as claimed in claim 10, wherein each of said memory cell rows comprises a word line and a plurality of memory cells whose control terminals are connected to said word line, each of said memory cell columns comprises a data line pair and a plurality of memory cells, whose input-output terminals are connected to one of the data lines of said data line pair, each of said first common data lines comprises a common data line pair, and each of said second common data lines comprises a common data line pair.

13. The semiconductor memory device as defined in claim 12, further comprising a first switch circuit coupled between said first memory array and said first common data lines, a second switch circuit coupled between said second memory array and said second common data lines, a first spare switch circuit coupled between said first spare memory array and said first common data lines, and a second spare switch circuit coupled between said second spare memory array and said second common data lines, and wherein said second selection means comprises a first address decoder producing selection signals to be supplied to said first switch circuit, and a second address decoder producing selection signals to be supplied to said second switch circuit, and wherein the operation of said first spare switch circuit is controlled by said first selection signal, and the operation of said second spare switch circuit is controlled by said second selection signal.

14. The semiconductor memory device as defined in claim 13, wherein said first switch circuit connects a plurality of data line pairs to a plurality of corresponding first common data line pairs to which said first amplifier means are connected, respectively, and which are designated by said selection signals produced from said first address decoder, and said second switch circuit connects a plurality of data line pairs to a plurality of corresponding second common data line pairs to which said second amplifier means are connected, respectively, and which are designated by said selection signals produced from said second address decoder, and wherein said first spare switch circuit connects a plurality of line pairs in said first spare memory array to a plurality of corresponding first common data line pairs, respectively, upon receiving said first selection signal, and said second spare switch circuit connects a plurality of data line pairs in said second spare memory array to a plurality of corresponding second common data lines, respectively, upon receiving said second selection signal.

15. The semiconductor memory device as defined in claim 14, wherein each of said first switch circuit, second switch circuit, first spare switch circuit and second spare switch circuit comprises switch MOSFETs interposed between respective data lines and corresponding common data lines.

16. The semiconductor memory device as defined in claim 13, wherein each of said memory cells comprises a capacitor and a MOSFET whose gate electrode is connected to said control terminal, one of its electrodes being connected to said input-output terminal and the other being connected to said capacitor.

19. The semiconductor memory device as defined in claim 16, further comprising a timing circuit, and wherein said control means comprises means receiving a timing signal produced from said timing circuit and for generating a first timing signal for controlling the operation of said first amplifier means and a second timing signal for controlling the operation of said second amplifier means.

20. A semiconductor memory device comprising:

first and second memory arrays, each having a plurality of memory cells formed along rows and columns;

first selection means for selecting at least one memory cell column indicated by first address signals from said first and second memory arrays;

a first common data line for receiving data of a memory cell in the memory cell column selected by said first selection means from said first memory array;

a second common data line for receiving data of a memory cell in the memory cell column selected by said first selection means from said second memory array;

a spare memory comprising at least one memory cell column formed with a plurality of memory cells, and providing data of a memory cell in said spare memory to said first common data line in response to a predetermined selection signal;

first amplifier means coupled to said first common data line, and operating in response to the selection of a memory cell from said first memory array so that data on said first common data line is amplified by said first amplifier means;

second amplifier means coupled to said second common data line, and operating in response to the selection of a memory cell from said second memory array so that data on said second common data line is amplified by said second amplifier means;

redundancy means receiving second address signals comprising at least said first address signals, and for generating a control signal when said second address signals are address signals which select a defective memory cell column from either one of said first and second memory arrays; and

control means responsive to said control signal, for generating said predetermined selection signal, for inhibiting the selection of a memory cell column from said first memory array, and for generating a timing signal for operating said first amplifier means so that data of a memory cell in said spare memory instead of the defective memory cell column in either one of said first and second memory arrays is amplified by said first amplifier means.

21. The semiconductor memory device as defined in claim 20, wherein each of said memory cell columns comprises a data line pair and a plurality of memory cells, each of said memory cells having an output terminal coupled to one of the data lines of said data line pair, and wherein each of said first and second common data lines comprises a common data line pair.

22. The semiconductor memory device as defined in claim 21, wherein said redundancy means comprises a memory circuit for storing address signals which indicate said defective memory cell column from either one of said first and second memory arrays, and a comparison circuit for comparing said address signals stored in said memory circuit with said second address signals and for generating said control signal when said second address signals are address signals which select said defective memory cell column from either one of said first and second memory arrays.