Adaptive rate multiplexer-demultiplexer
First Claim
1. A multiplexer-demultiplexer for multiplexing a plurality of digital subchannels into a transmit bit stream on a fixed rate channel and for demultiplexing a receive bit stream from the fixed rate channel into the plurality of digital subchannels, the transmit and receive bit streams being organized in frames having a frame structure consisting of a fixed number of bits, the number of bits per frame being determined as a function of the rates of the digital subchannels and the rate of the fixed rate channel, said multiplexer-demultiplexer comprising,memory means for storing the bit assignment pattern of the frame structure,plural transmit and receive bit storage means, one transmit and one receive bit storage means associated with each one of the digital subchannels, each transmit bit storage means for storing bits from its associated digital subchannel to be multiplexed into the transmit bit stream and each receive bit storage for storing bits from the receive multiplexed bit stream to be distributed to its associated digital subchannel,bit distribution means connected to said memory means, said plural transmit and receive bit storage means, and the fixed rate channel, for selecting in accordance with said stored bit assignment pattern bits from said plural transmit bit storage means to form said transmit bit stream and for distributing in accordance with said stored bit assignment pattern bits in said receive bit stream to said plural receive bit storage means, andplural clocking means, one clocking means associated with each one of the digital subchannels for generating a clock signal that clocks bits between the one digital subchannel and the transmit and receive bit storage means associated with that one digital subchannel at the rate of the one subchannel, each of said plural clocking means each responsive to the frame structure for automatically generating its clock signal at the rate of the associated digital subchannel,wherein said multiplexer-demultiplexer is adaptive to the frame structure stored in said memory means as a function of the rates of the plural digital subchannels and the fixed rate channel.
1 Assignment
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Accused Products
Abstract
A plurality of various rate digital subchannels are multiplexed onto a fixed rate channel by arranging the data bits from the subchannels into a framing structure consisting of j sets of i-tuples for ij bits per frame where the parameters i and j are mathematically determined as a junction of the rates of the subchannels and the rate of the fixed channel. Framing is maintained by setting each bit in the first i-tuple to ZERO and the last bit in each other i-tuple to ONE. A multiplexer-demultiplexer is described which is adaptive to the rates of the subchannels and the fixed channel in this frame structure and which can therefore be employed for any mix of subchannel and fixed channel rates. The multiplexer-demultiplexer includes a memory (204) for storing the bit assignment pattern for a frame structure configured for a particular mix of subchannel rates; plural subchannel interfaces (201-0--201-11) for storing bits directed to and from each channel and for clocking these bits onto and off the subchannels at their subchannel rates; and a kernel (203) which selects bits stored in the subchannel interfaces to form the multiplexed bit streams and distributes bits from the fixed channel to the subchannel interfaces in accordance with the stored bit assignment pattern. When a new bit assignment pattern is stored in the memory derived from a new combination of subchannel and fixed channel rates, the multiplexer-demultiplexer automatically adapts to the new frame structure and channel rates.
49 Citations
26 Claims
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1. A multiplexer-demultiplexer for multiplexing a plurality of digital subchannels into a transmit bit stream on a fixed rate channel and for demultiplexing a receive bit stream from the fixed rate channel into the plurality of digital subchannels, the transmit and receive bit streams being organized in frames having a frame structure consisting of a fixed number of bits, the number of bits per frame being determined as a function of the rates of the digital subchannels and the rate of the fixed rate channel, said multiplexer-demultiplexer comprising,
memory means for storing the bit assignment pattern of the frame structure, plural transmit and receive bit storage means, one transmit and one receive bit storage means associated with each one of the digital subchannels, each transmit bit storage means for storing bits from its associated digital subchannel to be multiplexed into the transmit bit stream and each receive bit storage for storing bits from the receive multiplexed bit stream to be distributed to its associated digital subchannel, bit distribution means connected to said memory means, said plural transmit and receive bit storage means, and the fixed rate channel, for selecting in accordance with said stored bit assignment pattern bits from said plural transmit bit storage means to form said transmit bit stream and for distributing in accordance with said stored bit assignment pattern bits in said receive bit stream to said plural receive bit storage means, and plural clocking means, one clocking means associated with each one of the digital subchannels for generating a clock signal that clocks bits between the one digital subchannel and the transmit and receive bit storage means associated with that one digital subchannel at the rate of the one subchannel, each of said plural clocking means each responsive to the frame structure for automatically generating its clock signal at the rate of the associated digital subchannel, wherein said multiplexer-demultiplexer is adaptive to the frame structure stored in said memory means as a function of the rates of the plural digital subchannels and the fixed rate channel.
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10. A multiplexer for multiplexing a plurality of digital subchannels into a transmit bit stream on a fixed rate channel, the transmit bit stream being organized in frames having a frame structure consisting of a fixed number of bits, the number of bits being determined as a function of the rates of the digital subchannels and the rate of the fixed rate channel, said multiplexer comprising,
memory means for storing the bit assignment pattern of the frame structure, plural bit storage means each one associated with one of the digital subchannels, each storage means for storing bits from the one digital subchannel to be multiplexed into the transmit bit stream, bit distribution means connected to said memory means, said plural bit storage means, and the fixed rate channel, for selecting in accordance with said stored bit assignment pattern bits from said plural bit storage means to form said transmit bit stream, and plural clocking means, one clocking means associated with each of the digital subchannels for generating a clock signal that clocks bits between the one digital subchannel and the bit storage means associated with that one subchannel at the rate of the one subchannel, each of said plural clocking means responsive to the frame structure for automatically generating its clock signal at the rate of the associated digital subchannel, wherein said multiplexer is adaptive to the frame structure stored in said memory means as a function of the rates of the plural digital subchannels and the fixed rate channel.
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19. A demultiplexer for demultiplexing a receive bit stream on a fixed rate channel into a plurality of digital subchannels, the receive bit stream being organized in frames having a frame structure consisting of a fixed number of bits, the number of bits being determined as a function of the rates of the digital subchannels and the rate of the fixed rate channel, said demultiplexer comprising,
memory means for storing the bit assignment pattern of the frame structure, plural bit storage means each one associated with one of the digital subchannels, each storage means for storing bits from the receive multiplexed bit stream to be distributed to its associated subchannel, bit distribution means connected to said memory means, said plural bit storage means, and the fixed rate channel, for distributing in accordance with said stored bit assignment pattern bits in said receive bit stream to said plural bit storage means, and plural clocking means, one clocking means associated with each of the digital subchannels for generating a clock signal that clocks bits between the one digital subchannel and the bit storage means associated with that one subchannel at the rate of the one subchannel, each of said plural clocking means responsive to the frame structure for automatically generating its clock signal at the rate of the associated digital subchannel, wherein said demultiplexer is adaptive to the frame structure stored in said memory means as a function of the rates of said plural digital subchannels and fixed rate channel.
Specification