Pipelined, line buffered real-time color graphics display system

• US 4,658,247 A
• Filed: 07/30/1984
• Issued: 04/14/1987
• Est. Priority Date: 07/30/1984
• Status: Expired due to Fees

• Current Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Original Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Inventors: Gharachorloo, Nader
• Primary Examiner(s): Brigance, Gerald L.
• Assistant Examiner(s): Brier, Jeffery A.
• Application Number:
  US06/635,806
• Time in Patent Office: 988 Days
• Field of Search: 340/701, 340/703, 340/744, 340/747, 340/750, 364/131, 364/133, 364/136, 364/518, 364/520, 364/521, 364/522
• US Class Current: 345/560
• CPC Class Codes: G06T 15/80 Shading
• CPC Class Codes: G09G 5/42 characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen

Abstract

A color graphics system for displaying a plurality of polygons, based upon polygon commands supplied by a host computer. The system accepts the commands from the host and circulates them in a circular queue past a polygon processor or "painter'"'"'s station" which examines each to see if it is on the line currently being processed. If the polygon is on the line, a line command or "micropainter" is generated and placed in a pipeline comprising a plurality of microprocessors, one for each picture element ("pixel") in the video scan line. The micropainters are passed from processor to processor down the pipeline, in synchronization with the video scan. Each pixel processor examines the micropainter and stores its color if the painter affects the pixel on the scan line which is assigned to that processor, and, in one embodiment, if the micropainter is painting a polygon which is higher (less in depth) than the last polygon whose color was stored in the processor. A special command, called a "microinspector" is introduced into the pipeline once each scan, and causes each pixel processor in turn to output its stored video information to a video refresh processor, which drives the display.

Claims

1. A real-time image processing system for creating color video images on a raster-scan display made up of a plurality of scan lines, each scan line made up of a plurality of picture elements ("pixels"), the image comprising a plurality of polygons, the polygons being based upon a plurality of data elements supplied from a host computer, each data element representing a single polygon to be displayed, the data element specifying at least beginning and ending scan lines, beginning and ending pixel locations on at least one line, and color for each polygon, comprising:

(a) circulating ring means for storing and sequentially accessing a plurality of data elements, comprising;

(1) storage means for storing a plurality of data elements in discrete locations;

(2) input means for accepting data elements for the host computer and placing them in locations in the storage means;

(3) memory management means for organizing the storage means, whereby each data element stored in the storage means may be individually accessed as if in a circular queue, whereby the storage means is organized by the memory management means as a first-in-first-out memory in which the first data element in the storage means is sequentially accessed immediately after the last data element;

(4) polygon processing for decomposing the polygon represented by the data elements accessed by the memory management means into scan lines;

(b) video refresh means for creating the video image on the raster-scan display, comprising;

(1) input means for accepting pixel data;

(2) video output means for generating video displays from the pixel data supplied by the input means;

(3) synchronization means for indicating the scan line and pixel being generated, having a clock input for synchronization pulses, and current pixel and line indication output means for indicating the point in the image being currently written to the raster-scan display;

(c) the polygon processing means comprising;

(1) input register means for accepting a data element representing a polygon from the storage means via the memory management means;

(2) selection means for examining the data element in the input register means and determining if at least part of the polygon represented by the element is located on the scan line currently being created, having a data input connected to the input register means, a synchronization input connected to the screen synchronization means of the video refresh means, and an active output indicating that at least part of the data element is located on the current scan line;

(3) painter station means for creating line buffer instructions, having a first input connected to the input register means, a second input connected to the active output of the selection means, a third input connected to the synchronization means of the video refresh means and output means adapted to producing micropainter, null, or microinspector instructions for loading into a line buffer pipeline;

(4) output register means for replacing a data element into the storage means via the memory management means;

(5) processing means for transferring data elements from the input register means to the output register means;

(6) the painter station being adapted to produce micropainter instructions at the output means if the active output of the selection means indicates that the data element in the input register means is active;

the micropainter comprising at least the addresses of the leftmost and rightmost pixels on the current line on which the polygon represented by the data element appears, and the color of the polygon;

(7) the painter station being adapted to produce null instructions at the output means if the active output of the selection means is not active, the null instructions being instructions which do not have any active pixels or are identical to the last micropainter instruction produced by the painter station, whereby no change in the scan line is caused by the instruction;

(8) the painter station being adapted to produce microinspector instructions at the output means if the synchronization means of the video refresh means indicates a new line is to be displayed, the microinspector comprising at least a refresh flag;

(d) line buffer pipeline means comprising;

(1) a plurality of pixel processors, one for each pixel on a scan line, comprising;

(a) input register means for accepting an instruction, comprising storage for at least a beginning address and an ending address, a color, and a fresh flag;

(b) output register means for transmitting an instruction, comprising storage for at least a beginning address and an ending address, a color and a refresh flag;

(c) pixel buffer means for storing the color of a pixel, having a color input connected to the color storage of the input register means, a load input, a read input connected to the refresh flag storage of the input register means, and a video output;

(d) processing means for copying the instruction in the input register means into the output register means, comprising a clock input, a data input connected to the input register, and a data output connected to the output register, whereby a signal at the clock input causes the data in the input register to be copied to the output register;

(e) identifier means for indicating which pixel in the scan line is processed by the pixel processor;

(f) comparator means for determining if the instruction in the input register affects the pixel processor by the pixel processor, having inputs connected at least to the beginning and ending addresses in the input register means, and an active output adapted to indicate active if the pixel is addressed by the instruction, the active output being connected at least to the load input of the pixel buffer means;

(g) the pixel buffer means being adapted to storing the color from the color input when the load input is active;

whereby the color from the input register is stored if the instruction affects the pixel processed;

(h) the pixel buffer means being adapted to output the color stored to the video output of the pixel buffer means when the read input is active, whereby the stored color output upon receipt of a microinspector instruction;

(2) video reading means for conveying video information to the video refresh means, having a plurality of inputs connected to the video outputs of the pixel buffer means, and an output connected to the input means of the video refresh means;

(3) the input register means of the first pixel processor being connected to the output means of the painter station means;

(4) the input register means of each pixel processor except the first being connected to the output register means of the preceding pixel processor in the pipeline means;

(e) clock means for generating clock signals on the pipeline for synchronization to the video refresh means, having an output connected at least to the clock input of the processing means of the pixel processors, and to the clock input of the synchronization means of the video refresh means whereby the instructions in the pipeline advance along the the pipeline from pixel processor to pixel processor, one step for each clock signal;

the clock signals being synchronized such that the time for an instruction to pass through all the pixel processors on the pipeline is exactly equal to the time for one scan line to be generated in the video display.

2. The image processing system of claim 1 in which the video image represents polygons at a plurality of depths relative to each other, such that higher polygons may wholly or partly cover open lower polygons, and the data elements supplied by the host computer are adapted to being coded by the host computer with code means for specifying the depth of at least one pixel location in the polygon, and the micropainter instructions further comprise information for determining the depth of at least one point on the scan line.

3. The image processing system of claim 2 in which the pixel processors of the line buffer pipeline means further comprise:

a. the input register means further comprising a depth code for indicating the depth of the polygon at that pixel;

b. the output register further comprising a depth code for indicating the depth of the polygon at the next pixel;

c. Z buffer means for storing the depth of the last micropainter which caused its color to be stored in the pixel buffer means;

d. depth comparator means for comparing the depth of the micropainter being processed by the pixel processer to the depth stored in the Z buffer, having a first input connected to the depth code of the input register, a second input connected to the Z buffer, and a load output adapted to indicate active if the micropainter specifies a depth which is higher than the depth stored in the Z buffer;

e. the pixel buffer means further comprising a depth load input connected to the load output of the depth comparator means;

f. the pixel buffer means being further adapted to storing the color from the color input only when both the load input and depth load input are active.

4. The image processing system of claim 3 in which:

(a) the micropainter instruction further comprise increment information for indicating the change in depth of the polygon along the line;

b. the processing means for transferring data elements of the pixel processing means of the line buffer pipeline further comprising means for adding the increment to the depth code of the input register means before copying it to the output register means, whereby the depth of the polygon may slope from one end of the line to the other.

5. The image processing system of claim 1 in which the video image represents polygons in a plurality of depths relative to each other, such that higher polygons may wholly or partly cover lower polygons, and data elements supplied by the host computer are coded by the host computer with code means for specifying the time the polygon is to be written, whereby polygons to be written later in time may write over polygons to be written earlier in time.

6. The image processing system of claim 1, in which the video image represents polygons which may be shaded in color across the polygon, in which:

(a) the data elements supplied from the host computer further comprise a first color increment code means for specifying the change in color per line from the top of the polygon to the bottom, and a second increment code means for specifying the change in color of the polygon from left to right;

(b) the processing means of the polygon processing means further comprising adder means for incrementing the color in the polygon instruction by the first color increment means before transferring the data elements from input register means to the output register means;

(c) the micropainter instructions further comprising a color increment code;

(d) the processing means of the pixel processors of the line buffer means further comprising adder means for adding the increment code of the micropainter to the color before copying the micropainter instruction in the input register means to the output register means, whereby the color of the polygon is made to change across the line being written.

7. The image processing system of claim 1 in which there are a plurality of line buffer pipeline means, adapted to processing more than one line in parallel, and in which the polygon processing means comprises a plurality of painter station means, one for each line buffer means.

8. The image processing system of claim 1 in which the number of pixel processors is an intergral fraction of the number of pixels on the screen line, and in which the pixel processors further comprise:

(a) the output register means of the last pixel processor being connected to the input register means of the first pixel processor whereby instructions in the line buffer pipeline may circulate from the last pixel processor back to the first one;

(b) the identifier means of the pixel processors further comprising means for changing a pixel which the pixel processor is processing, whereby each pixel processor may be caused to process a plurality of pixel information;

(c) the identifier means further comprising means for changing the identification of the pixel being processed when the microinspector instruction is received.

9. The image processing system of claim 1 in which the pixel processors of the line buffer pipeline means are connected in pairs, the input register means of each pair of pixel processors being connected in parallel, each pair comprising the pixel processor for a odd numbered pixel and the adjoining even numbered pixel, whereby each pair of pixel processors may work on the micropainter instructions in parallel.

10. The image processing system of claim 1 in which the video reading means of the line buffer pipeline means comprises a global bus connected to all of the pixel processing means in parallel having an output connected to the video refresh means input means.

11. The image processing system of claim 1 in which the video reading means comprises:

(a) video input register means in each of the plurality of pixel processors;

(b) video output register means in each of the plurality of pixel processors;

(c) processing means for copying the instruction in the video input register means into the video output register means, comprising a data input connected to the video input register means and a data output connected to the video output register means, whereby a signal of the clock input causes the data in the input video register to be copied into the output video register;

(d) the clock input of the video processors means being connected to the output of the clock means, whereby the video information is passed from the input register means to the output video means in synchronization with the instructions being copied from the input register means into the output register means by the processing means of the pixel processor;

(e) the input register means of each pixel processor means except the last being connected to the output video register means of the next higher numbered pixel processor;

(f) the video output register means of the lowest numbered pixel processor being connected to the input means of the video refresh means.

12. The image processing system of claim 1 in which the input means of the circulating ring means comprises:

(a) first-in-first-out buffer means for accepting and storing data elements from the host computer, having an input for new data elements connected to the host computer, and an output for outputting the oldest data elements in the buffer means;

(b) selector means for placing data elements in locations in the storage means, comprising an input connected to the output of the first-in-first-out buffer means, and an output adapted to placing data elements in selected positions in the storage means.

13. The image processing system of claim 12 in which the selector means of the input means of the circulating ring means further comprises comparison means for comparing at least the beginning scan lines of the output data elements from the first-in-first-out buffer means with a data element in the circular queue in the storage means, whereby data elements from the host may be inserted into the circular queue in order at least of beginning scan lines.

14. The image processing system of claim 13 in which the data elements are stamped by the host with an addition value representing the time or depth priority of the data element, and the comparison means compares based on both beginning scan line and the time or depth priority, whereby the data elements in the circular queue are sorted in order of beginning scan line and depth.