Computer network operating method and apparatus for detecting and exploiting data collisions to merge read transactions

• US 4,658,250 A
• Filed: 06/15/1984
• Issued: 04/14/1987
• Est. Priority Date: 06/15/1984
• Status: Expired due to Fees

• Current Assignee: Douglas G. Nering, James L. Bucanek
• Original Assignee: Douglas G. Nering, James L. Bucanek
• Inventors: Nering, Douglas G., Bucanek, James L.
• Primary Examiner(s): YUSKO, DONALD
• Application Number:
  US06/621,070
• Time in Patent Office: 1,033 Days
• Field of Search: 340/825.5, 340/825.05, 340/825.51, 370/85, 370/94
• US Class Current: 370/462
• CPC Class Codes: G06F 13/374 using a self-select method with individual priority code comparator

Abstract

In a computer network including a plurality of processors coupled to a data bus, ones of the processors contending for the data bus to output data requests each output priority byes of their transmission header packets as a series of data bits. Every contending processor sequentially reads data present on the data bus. Each processor that reads a "one" on the bus corresponding to a "zero" output by that processor interprets this as a data collision yields the bus for data transmission purposes, but continues to read all data appearing on the data bus and compares it with corresponding bits of its own transmission header packet. Only the processor having highest priority detects no data collision, and continues to output its data request. If any other contending processor determines that the data request of the highest priority processor is identical or sufficiently similar to its own, it merges its request with that of the highest priority processor by reading the resulting data, thereby reducing waiting time especially in file-intensive operations.

Claims

1. A computer network comprising:

(a) a bus, including a bus conductor;

(b) a plurality of processors coupled to said bus, some or all of which processors contend for control of said bus in order to transmit transmission header information, including priority header information followed by transaction header information, via said bus to a destination address, said priority header information in each of said processors including a plurality of bits arranged as priority code;

(c) data asserting means in each of said processors causing said contending processors to each concurrently assert corresponding bits of their respective priority codes on said bus in order of decreasing bit significance, such that if any of said corresponding priority code bits is at a first logic level, said first logic level appears on said bus conductor and otherwise a second logic level appears on said bus conductor;

(d) priority bit reading means in each of said processors for causing each contending processor to read the priority bit logic levels appearing on said bus conductor;

(e) priority bit comparing means in each of said processors for causing each contending processor to compare the logic levels of the bits of its priority code to corresponding logic levels of bits read on said bus conductor in order of decreasing bit significance to detect the occurrence of any data mismatches therebetween;

(f) mismatch data gating means in each of said processors for causing any of said contending processors for which a data mismatch is detected to immediately stop asserting further bits of its transmission header information;

(g) transaction data transmission means in each of said processors for causing a highest priority one of said contending processors which does not detect a data mismatch during transmission of its priority header information to transmit its transaction header information on said bus;

(h) transaction header reading and comparing means for causing each other one of said contending processors to read the bits of data of said transaction header information transmitted by said highest priority contending processor on said data bus and compare those bits with respective corresponding bits of the transaction header information of that contending processor to detect any mismatches therebetween; and

(i) mergeability determination means in each of said processors responsive to said transaction header reading and comparing means for causing each of said other ones of said contending processors to determine, in response to its comparing of its own transaction header information with that transmitted on said bus by said highest priority contending processor, whether a first transaction specified by the transaction header information of that contending processor can be merged with a second transaction specified by the transaction header information of said highest priority contending processor.

2. The computer network of claim 1 including merging means in each of said processors responsive to said mergeability determination means therein for causing that processor to read all of the data appearing on said data bus during said second transaction.

3. The computer network of claim 2 including priority modification means in each of said contending processors for modifying the priority code of that contending processor before that contending processor can contend for said bus.

4. The computer network of claim 3 wherein each of said processors includes a computer and an interface circuit coupling that couples that computer to said bus, said bus including a bidirectional serial data bus including said bus conductor, a ready signal conductor, and an acknowledge signal conductor, and a busy signal conductor.

5. The computer network of claim 4 wherein said interface circuit includes shift register circuit means for transferring data in parallel format between said interface circuit and said computer and for effectuating transfer of data in serial format between said bus conductor and said interface circuit.

6. The computer network of claim 5 wherein said interface circuit includes local station address means for storing a permanent local address code of said processor and address comparison means coupled to said shift register circuit means and said local address means for producing a predetermined signal if an address code that has been input into said shift register circuit means from said bus conductor matches said local address code.

7. The computer network of claim 6 wherein said interface circuit includes comparison circuit means for sequentially comparing corresponding bits of transmission header information written into said shift register circuit means by said computer and transmission header information appearing on said bus conductor and producing a mismatch signal in response to a mismatch between said corresponding bits, and storage means responsive to said comparison circuit means and coupled to said computer for storing information indicative of the occurrence of said mismatch and gating circuit means coupled to said storage means, said bus conductor and said shift register circuit means for preventing any data having said first logic level from being asserted by that contending processor onto said bus conductor.

8. The computer network of claim 7 wherein said interface circuit includes handshaking logic circuit means coupled to said bus conductor, said busy signal conductor, said Ready signal conductor, said Acknowledge signal conductor, said shift register circuit means, and said storage means for effectuating handshaking operations to synchronize transfer of said transmission header information on said bus conductor.

9. A method of operating a computer network including a bus and a plurality of processors, some or all of which contend for control of said bus in order to transmit transmission header information, including priority header information followed by transaction header information, via said bus to a destination address, said priority header information in each of said processors including a plurality of priority bits arranged as a priority code, said method comprising the steps of:

(a) causing each of said contending processors to concurrently assert a most significant bit of its priority code on said bus such that if any of said most significant priority code bits is at a first logic level, said first logic level appears on a conductor of said bus and otherwise a second logic level appears on said bus conductor;

(b) causing each contending processor to read the logic level appearing on said bus conductor;

(c) causing each contending processor to compare the logic level of the most significant bit of its priority code to the logic level read in step (b) to determine if a data collision has occurred;

(d) causing any of said contending processors detecting a data collision to stop asserting bits of its transmission header information;

(e) repeating steps (a) through (d) for the remaining bits of said priority codes in order of decreasing bit significance;

(f) causing a highest priority one of said contending processors which does not detect a data collision to transmit its transaction header information on said bus, and also causing each other one of said contending processors to read the bits of data appearing on the bus and compare those bits with respective corresponding bits of the transaction header information of that contending processor to detect any mismatches therewith; and

(g) causing each of said other ones of said contending processors to determine, in response to said comparing of step (f), if a first transaction specified by the transaction header information of that contending processor can be merged with a second transaction specified by the transaction header information of said highest priority contending processor by determining if the data to be conducted on said bus in effectuating said first transaction is identical to or is a subset of the data that would be conducted on said bus in effectuating said second transaction.

10. The method of claim 9 further including the step of causing each of said other ones of said contending processors to determine, in response to said comparing of step (f), if a first transaction specified by the transaction header information of that contending processor is mergeable with a second transaction specified by the transaction header information of said highest priority contending processor by determining if the data to be conducted on said bus in effectuating said first transaction is identical to the data that would be conducted on said bus in effectuating said second transaction.

11. The method of claim 9 including causing said highest priority contending processor to write information onto said bus and read information from said bus as necessary to effectuate performing of said second transaction.

12. The method of claim 11 including causing each of said other ones of said contending processors for which said determining is affirmative to merge said first transaction with said second transaction by continuing to read data appearing on said bus during said second transaction.

13. The method of claim 12 including causing said highest priority contending processor to modify its priority code to a different value.

14. The method of claim 12 including causing each contending processor which does not merge its transaction with said second transaction to modify its priority code to a different value.

15. The method of claim 11 wherein the bits of said transaction header information are serially asserted on said bus conductor.

16. The method of claim 15 wherein said bus includes a pair of handshaking signal conductors for respectively conducting a ready signal responsive to any of said contending processors for indicating when data on said bus conductor is valid and an acknowledge signal generated by the last one of said other contending processors to read data on said bus conductor in response to said ready signal.

17. A method of operating a computer network including a bus and a plurality of processors, some of which are contending for control of said bus in order to transmit transmission header information, including priority header information followed by transaction header information, via said bus to a destination address, said priority header information in each of said processors including a predetermined number of priority bits arranged as a priority code, said method comprising the steps of:

(a) causing each of said contending processors to concurrently assert the most significant bit of its priority code on said bus such that if any of said most significant priority code bits is a first logic level, said first logic level appears on a conductor of said bus, and otherwise a second logic level appears on said bus conductor;

(b) causing each contending processor to read the logic level appearing on said bus conductor;

(c) causing each contending processor to compare the logic level of the most significant bit of its priority code to the logic level read in step (b) to determine if a data collision has occurred;

(d) causing any of said contending processors detecting a data collision to stop asserting bits of its transmission header information;

(e) repeating steps (a) through (d) for the remaining bits of said priority codes in order of decreasing bit significance;

(f) causing a highest priority one of said contending processors which does not detect a data collision to transmit its transaction header information on said data bus, and also causing each other one of said contending processors to read the bits of data appearing on the data bus and compare those bits with respective corresponding bits of the transaction header information of that contending processor to detect any mismatches therewith;

(g) causing each of said other ones of said contending processors to determine, in response to said comparing of step (f) to determine whether a first transaction specified by the transaction header information of that contending processor can be merged with a second transaction specified by the transaction header information of said highest priority contending processor by determining if the data to be conducted on said bus in performing said first transaction is identical to or is a subset of the data that will be conducted on said bus in performing said second transaction;

(h) causing said highest priority contending processor to write information onto said bus and read information from said bus as necessary to effectuate performing of said second transaction;

(i) causing each of said other ones of said contending processors for which the determination of step (g) is affirmative to continue to read data appearing on said bus during said second transaction; and

(j) causing said highest priority contending processor to modify its priority code to a different value, and causing each contending processor which does not merge its transaction with said second transaction to modify its priority code to a different value.