WSI tester

• US 4,658,400 A
• Filed: 06/07/1984
• Issued: 04/14/1987
• Est. Priority Date: 06/07/1984
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Trilogy Computer Development Partners, Ltd.
• Inventors: Mozsgai, Steven I., Brown, Harold E., Chen, Jason C.
• Primary Examiner(s): Fleming, Michael R.
• Application Number:
  US06/618,095
• Time in Patent Office: 1,041 Days
• Field of Search: 371/25, 371/24, 371/20, 324/73 R, 364/200 MS File, 364/ 900 MS File
• US Class Current: 714/736
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory
• CPC Class Codes: G06F 11/181 Eliminating the failing redundant component
• CPC Class Codes: G06F 11/183 by voting, the voting not being performed by the redundant components
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]

Abstract

A test system including a data center, controller, interface, and device under test. The data center generates a test program which is applied to the device under test by the controller via the interface. The device under test includes circuitry structured for testing. The test system identifies the location of faulty elements on the device under test and stores these locations for use in a subsequent repair step.

Claims

1. A system for testing a device under test (DUT), having DUT I/O ports, with the DUT of the type including N identical logical circuit copies, each circuit copy including storage elements (SEs) and combinatorial elements (CEs) and with each logic circuit copy structured into circuit element groups (CEGs) including only CEs, with each CEG having a set of inputs coupled to input SEs and a single output, where each of the identical logical circuit copies are structured into identical, corresponding CEGs, said test system comprising:

a first test machine including N identical, corresponding first CEGs from each of the N circuit copies;

a first set of input SEs coupled to the input ports of said first CEGs of said first test machine;

a first voting logic circuit, having N input ports and N output ports, for generating a logic output signal at said N output ports, with the logic state of the output signal equal to the logic state of the majority of input signals received at said first voting logic circuit input ports;

first enabling means for controllably coupling the output port of each said first CEG in said first test machine to a respective one of the input ports of said first voting logic circuit;

a first set of N outputs SEs, with each output SE having an input port coupled to a respective one of the output ports of said voting logic circuit;

means for transferring the logic state stored in an SE in said first set of output SEs to the DUT I/O ports;

means for generating a test vector for setting the input states of said first set of input SEs to test said first test machine for faults and for transferring said test vector to the DUT I/O ports;

means for generating a pre-test output state, corresponding to said test vector, to set the output state of said first set of output SEs prior to fault testing and for transferring said pre-test output state to the DUT I/O ports;

means for generating an expected value post test output state;

means, coupled to the DUT I/O ports, for loading said test vector into the first set of input SEs;

means, coupled to the DUT I/O ports, for setting the output state of the first set of output SEs to said pre-test output state;

means, coupled to said first test machine, for clocking said first test machine through one machine cycle to generate a post-test output state; and

means, coupled to said DUT I/O ports, for comparing said post-test output state with said expected value post test output state to determine whether said first test machine has a fault.

2. The invention of claim 1 wherein said enabling means includes:

a first set of N MUXs having at least a first and second data input port, a data output port, a select port, an an inhibit port, with the output port of each CEG of the first test machine coupled to the first input port of a respective one of said N MUXs and with the output port of each MUX coupled to a respective input port of said voting circuit so that if a test machine has a fault the first CEGs may be sequentially coupled to said voting circuit by directing appropriate signals to the inhibit port to determine which first CEG has a fault.

3. The invention of claim 1 wherein said means for setting comprises:

an internal shift register, including the SEs of said logical circuit copies, coupling the DUT I/O ports to the input ports of said first set of N output SEs.

4. The invention of claim 1 or 3 further comprising:

a second test machine, including N identical second CEGs;

a second set of input Ses coupled to the input ports of the second CEGs of said second test machine;

a second voting logic circuit, having N input ports and N output ports;

second enabling means for controllably coupling the output port of each second CEG to a respective one of the input ports of said second voting logic circuit; and

a second set of N output SEs having input ports coupled to respective output ports of said second voting logic circuit.

5. The invention of claim 4 wherein said internal shift register comprises:

means coupling the output port of one of the SEs in said second set of output SEs to the second input port of one of said MUXs so that said first and second sets of output SEs may be configured as shift register elements by selecting the second input ports of said MUXs.