Peak demand limiter

• US 4,659,943 A
• Filed: 03/19/1986
• Issued: 04/21/1987
• Est. Priority Date: 03/19/1986
• Status: Expired due to Fees

• Current Assignee: Robert L. Virant
• Original Assignee: Robert L. Virant
• Inventors: Virant, Robert L.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Blum, Richard K.
• Application Number:
  US06/841,304
• Time in Patent Office: 398 Days
• Field of Search: 307/34, 307/35, 307/38, 307/39, 323/249, 323/250, 323/328, 323/329, 336/175
• US Class Current: 307/39
• CPC Class Codes: H02J 2310/60 Limiting power consumption in the network or in one section of the network, e.g. load shedding or peak shaving
• CPC Class Codes: H02J 3/14 by switching loads on to, or off from, network, e.g. progressively balanced loading
• CPC Class Codes: Y02B 70/3225 Demand response systems, e.g. load shedding, peak shaving
• CPC Class Codes: Y04S 20/222 Demand response systems, e.g. load shedding, peak shaving

Abstract

A peak demand limiter to monitor a plurality of electrical circuits and to selectively switch the circuit in a predetermined pattern based on priority selection comprises a load detection circuit coupled to a logic processor that generates and sends output data to control switches on preselected non-priority circuits.

Claims

1. A peak demand limiter circuit for controlling the overall load demand for electrical power in several load circuits by monitoring the same and their connection with a source of electrical power, the peak demand limiter circuit characterized by its monitoring mode that requires no power consumption in said mode, said peak demand limiter circuit comprising a saturable core transformer positioned around said load circuits and a rectifier circuit to modify a signal generated by said saturable core transformer upon any of said monitored load circuits reaching a pre-determined load level, a logic processor in connection with said rectifier circuit and driven by output power from said saturable core transformer via said rectifier circuit, a plurality of gate signal relays responsive to said logic processor, a primary load control circuit and a load triac in connection with said load circuits for interupting said series of said load circuits responsive in operation to said signal generated by said saturable core transformer, means for varying the pre-determined load level by increasing or decreasing amper turns on said saturable core transformers so that said saturable core transformer response can be varied.