Immersion type ISFET

• US 4,660,063 A
• Filed: 03/18/1985
• Issued: 04/21/1987
• Est. Priority Date: 03/18/1985
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Anthony, Thomas R.
• Primary Examiner(s): Edlow, Martin H.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/713,143
• Time in Patent Office: 764 Days
• Field of Search: 357/25, 357/55, 357/29, 357/23.15
• US Class Current: 257/253
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618

Abstract

Three-dimensional diode arrays have been produced in semiconductor wafers by a two-step process involving laser drilling and solid-state diffusion.

Holes are first produced in the wafer in various arrays by laser drilling. Under suitable conditions, laser drilling causes little or no damage to the wafer. Cylindrical P-N junctions are then formed around the laser-drilled holes by diffusing an impurity into the wafer from the walls of the hole. A variety of distinctly different ISFET devices is produced.

Claims

1. A nonplanar ISFET device comprising:

a semiconductor body of a first conductivity type having first and second opposing major surfaces and a plurality of high-aspect-ratio, closely-spaced bores extending into the body from the first major surface thereof, including a bore with a relatively large cross-section extending between the first and second major surfaces of the body and being centrally situated among the plurality of high-aspect-ratio bores;

first and second impurity regions of a second conductivity type in the body, each one comprising a plurality of impurity zones, each zone being substantially concentric with a respective one of the plurality of high-aspect-ratio bores and overlapping one or more neighboring zones, the first and second impurity regions being separated and longitudinally intersected by the relatively large cross-section bore;

first and second connection means making electrical contact to the first and the second impurity regions, respectively, from the first major surface of the body, and

an ion-sensitive insulating layer covering the inner surface of the relatively large cross-section bore.

2. The ISFET device of claim 1 wherein the first and the second connection means each comprise a metallic contact overlapping the first major surface of the body and being in contact with a respective one of the first and the second impurity regions.

3. The ISFET device of claim 1 wherein the ion-sensitive insulating layer comprises a thermally grown oxide layer covering the inner surface of the relatively large cross-section bore.

4. The ISFET device of claim 1 wherein the plurality of high-aspect-ratio bores are generally disposed along a straight line and the relatively large cross-section bore is centrally situated along the line.

5. The ISFET device of claim 1 wherein the plurality of high-aspect-ratio bores are generally disposed in an array having a plurality of regularly spaced rows and a plurality of regularly spaced columns and the relatively large cross-section bore is centrally situated in the array.

6. The ISFET device of claim 1 wherein the plurality of high-aspect-ratio bores extend completely through the thickness of the body between the first and the second major surfaces thereof, and each of the high-aspect-ratio bores are sealed with an appropriate sealing material.

7. The ISFET device of claim 1 wherein the plurality of high-aspect-ratio bores extend to within a predetermined distance of the second major surface of the body.

8. The ISFET device of claim 1 wherein the semiconductor body is monocrystalline silicon, the first conductivity type is P-type and the second conductivity type is N-type.

9. The ISFET device of claim 1 wherein the plurality of high-aspect-ratio bores are formed by laser drilling and, the relatively large cross-section bore is formed by laser drilling and selective etching.

10. The ISFET device of claim 1 wherein the plurality of high-aspect-ratio bores are formed by laser drilling and the relatively large cross-section bore is formed by laser drilling at increased laser power.

11. The ISFET device of claim 1 wherein the plurality of high-aspect-ratio bores are formed by laser drilling and the relatively large cross-section bore is formed by laser drilling of multiple overlapping bores.

12. The ISFET device of claim 2 wherein the semiconductor body is monocrystalline silicon, the first conductivity type is P-type and the second conductivity type is N-type.

13. The ISFET device of claim 2 wherein the plurality of high-aspect-ratio bores are formed by laser drilling and the relatively large cross-section bore is formed by laser drilling and selective etching.

14. The ISFET device of claim 2 wherein the plurality of high-aspect-ratio bores are formed by laser drilling and the relatively large cross-section bore is formed by laser drilling at increased laser power.

15. The ISFET device of claim 2 wherein the plurality of high-aspect-ratio bores are formed by laser drilling and the relatively large cross-section bore is formed by laser drilling of multiple overlapping bores.