Multiplexed digital correlator

• US 4,660,164 A
• Filed: 12/05/1983
• Issued: 04/21/1987
• Est. Priority Date: 12/05/1983
• Status: Expired due to Fees

• Current Assignee: The United States of America As Represented By The Secretary of Agriculture
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Leibowitz, Lawrence M.
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Shaw, Dale M.
• Application Number:
  US06/558,070
• Time in Patent Office: 1,233 Days
• Field of Search: 364/728, 375/96
• US Class Current: 708/422
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines

Abstract

A high speed multiplexed digital correlator device for correlating serial data against reference data. The device includes a plurality of digital correlators configured to operate in parallel with their operations overlapping in time. The serial data is divided between the plurality of correlators by multiplexing means. The outputs of the plurality of correlators are summed to produce an overall correlation output signal. Due to the multiplexed configuration, the individual correlators operate at a much lower rate than the data rate of the serial data to be correlated. Also disclosed are synchronized mutliplexed correlators including multiple multiplexed correlators for correlating serial data differing in phase relationship with the reference data against which it is to be correlated.

Claims

1. A high speed digital correlator system for correlating input data bits in a serial input data stream comprising:

k digital correlators coupled to operate in parallel and to receive data bits from said serial input data stream;

multiplexing means coupled to said k correlators for directing each input data bit in said input data stream into one of said k correlators, each of said k correlators receiving every kth bit in said data stream said multiplexing means includes a k-bit ring counter with a clock input and k outputs, each of said k outputs being coupled to supply an input enabling signal to a respective one of said k correlators, said clock input being adapted to receive a clock signal synchronized with the flow of data bits in said serial input data stream, said ring counter supplying an input enabling signal to one of said k outputs in synchronism with each data bit in said serial input data stream coupled to each of said k correlators for enabling the input of each data bit from said serial input data stream to one of said k correlators, each of said k correlators being enabled to receive every kth data bit from said serial input data stream; and

combining means coupled to receive the outputs of said k correlators for combining said outputs into a measure of overall correlation;

wherein each of said k correlators operates at 1/kth of the data rate of said input data stream.

2. A high speed digital correlator system for correlating input data bits in a serial input data stream comprising:

k digital correlators coupled to operate in parallel;

serial to parallel data converter means coupled to receive data bits from said serial input data stream for supplying said data bits to k parallel outputs, each of said k parallel outputs being coupled to a data input of a respective one of said k correlators;

timing circuit means coupled to receive a clock signal synchronized with the flow of data in said serial input data stream for dividing the frequency of said clock signal by k and for supplying the frequency divided clock signal to an enabling input each of said k correlators; and

combining means coupled to receive the outputs of said k correlators for combining said outputs into a measure of overall correlation;

wherein each of said k correlators operates at 1/6th of the data rate of said input data stream.

3. A high speed synchronized multiplexed digital correlator system for correlating data bits in a serial data stream against a reference word, comprising:

k digital correlators coupled to operate in parallel, each of said k correlators being coupled to receive data bits from said serial data stream, each correlator being coupled to receive a data enabling signal from said multiplexing means for enabling the input of data bits from said serial data stream into said correlator, each of said k correlators being adaptable to contain a portion of said reference word;

a k-bit ring counter including a clock input and k outputs, said clock input being adatable to receive a clock signal synchronized with the flow of data bits in said serial data stream, each of said k outputs being coupled to supply said data enabling signals to said k multiplexed correlators, said ring counter supplying a data enabling signal to one of said k outputs in synchronism with each data bit in said serial data stream;

delay means coupled to receive said ouputs of said ring counter and coupled to supply said data enabling signals to said k multiplexed correlators, said delay means delaying the data enabling signals supplied to each multiplexed correlator relative to the adjacent multiplexed correlators by one pulse interval of said clock signal;

first combining means coupled to receive the outputs of said k digital correlators for combining said outputs into a measure of overall correlation; and

second combining means coupled to receive the outputs of each of said k correlators for combining said correlator outputs to form an output for said multiplexed correlator.

4. A high speed synchronized multiplexed digital correlator system for correlating data bits in a serial stream against a reference word, comprising:

k digital correlators coupled to operatate in parallel, each correlator including a data input port coupled to receive data bits from said multiplexing means and including a data enabling input port coupled to receive data enabling signal from said multiplexing means, said data enabling signals gating data bits appearing at said data input ports into said correlators, each correlator being adaptable to receive a portion of said reference word;

serial to parallel data converter means coupled to receive data bits from said serial data stream for supplying said data bits in parallel form to parallel outputs, each of said k parallel outputs being coupled to a data input port of a respective correlator in each multiplexed correlator, said k parallel outputs being coupled to the correlators in each of said k multiplexed correlators in a different order such that all of said k possible synchronization possibilities with said reference word occur in said k multiplexed correlators;

a k-bit ring counter including a clock input and k outputs, said clock input being adaptable to receive a clock signal synchronized with the flow of data bits in said serial data stream, said ring counter supplying a data enabling signal to one of said k ring counter outputs in synchronism with each data bit in said serial data stream, each multiplexed correlator being coupled to receive data enabling signals from one of said k ring counter outputs, said data enabling signald supplied to each multiplexed correlator being supplied to the data enabling input ports of each correlator therein;

first combining means coupled to receive the outputs of said k digital correlators for combining said outputs into a measure of overall correlation;

second combining means coupled to receive the outputs of each of said k correlators for combining said correlator outputs to form an output for the multiplexed correlator; and

summation means for adding the outputs of said k correlators.