Semiconductor memory device with switching for redundant cells

• US 4,660,179 A
• Filed: 12/17/1984
• Issued: 04/21/1987
• Est. Priority Date: 12/16/1983
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Aoyama, Keizo
• Primary Examiner(s): Moffitt, James W.
• Application Number:
  US06/682,515
• Time in Patent Office: 855 Days
• Field of Search: 365/200, 371/10
• US Class Current: 365/200
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

A organization for multi-bit output includes a plurality of memory cell groups and a plurality of data buses, each of which belongs to each of the groups, wherein one of memory cells in each memory cell groups are selected at the same time. A semiconductor memory device includes a plurality of groups of redundant cells one of which can replace a group of memory cells which comprise a defective memory cell, and switching circuits which selectively connect one of the groups of the redundant cells to the data bus belonging to one of the groups of memory cells. The switching circuit can connect the one of groups of the redundant cells to one of the data buses belonging to any of the cell groups.

Claims

1. In an organization for multi-bit output which comprises a plurality of memory cell groups and a plurality of data buses, each of which belongs to each of said groups, wherein one of memory cells in each memory cell groups are selected at the same time, a semiconductor memory device comprising;

a plurality of groups of redundant cells one of which can replace a group of memory cells which comprise a defective memory cell;

switching circuits which selectively connect one of said groups of the redundant cells to the data bus belonging to one of said groups of memory cells, so that said switching circuit can connect said one of said groups of said redundant cells to one of said data buses belonging to any of said cell groups; and

wherein said switching circuits comprise a first switch which is connected between data buses corresponding to a first group of redundant cells and a second group of redundant cells, a second switch which is connected between data buses corresponding to a first cell block and said first group of redundant cells and a third switch which is connected between data buses corresponding to a second cell block and said second group of redundant cells.

2. The semiconductor memory device according to claim 1, wherein, when the first group of redundant cells is linked to a first cell block, said first switch is opened and said second switch is closed, and when the first group of redundant cells and the second group of redundant cells are linked to said first cell block, said first switch, and said second switch are closed and said third switch is opened.

3. A semiconductor memory device according to claim 2, wherein said first, second and third switches are formed by a field effect transistor, and each of said switching circuits includes a ROM element.

4. A semiconductor memory device according to claim 3, wherein each of said ROM elements includes a series circuit of a high resistance and a fuse formed by poly-crystalline silicon connected between an electric source and ground, and when said fuse is melted, the voltage of said electric source is supplied to a control gate of said field effect transistor so that said field effect transistor is placed in an ON state.