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Semiconductor memory device with switching for redundant cells

  • US 4,660,179 A
  • Filed: 12/17/1984
  • Issued: 04/21/1987
  • Est. Priority Date: 12/16/1983
  • Status: Expired due to Term
First Claim
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1. In an organization for multi-bit output which comprises a plurality of memory cell groups and a plurality of data buses, each of which belongs to each of said groups, wherein one of memory cells in each memory cell groups are selected at the same time, a semiconductor memory device comprising;

  • a plurality of groups of redundant cells one of which can replace a group of memory cells which comprise a defective memory cell;

    switching circuits which selectively connect one of said groups of the redundant cells to the data bus belonging to one of said groups of memory cells, so that said switching circuit can connect said one of said groups of said redundant cells to one of said data buses belonging to any of said cell groups; and

    wherein said switching circuits comprise a first switch which is connected between data buses corresponding to a first group of redundant cells and a second group of redundant cells, a second switch which is connected between data buses corresponding to a first cell block and said first group of redundant cells and a third switch which is connected between data buses corresponding to a second cell block and said second group of redundant cells.

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