Semiconductor memory having multiple level storage structure

• US 4,661,929 A
• Filed: 12/24/1984
• Issued: 04/28/1987
• Est. Priority Date: 12/23/1983
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Horiguchi, Masashi, Nakagome, Yoshinobu, Aoki, Masakazu, Ikenaga, Shinichi, Shimohigashi, Katsuhiro
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/686,018
• Time in Patent Office: 855 Days
• Field of Search: 365/149, 365/182, 365/189, 365/230
• US Class Current: 365/149
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

In a semiconductor memory includes a memory array consisting of a plurality of memory cells respectively having at least one storage capacitor, an addressing circuit which designates location of each memory cell, data lines which transmit data connected to said memory cells and data writing and reading circuits connected to said data lines. The semiconductor memory has a multiple level storage structure. In particular, the memory includes an arrangement for sequentially applying, on a time series basis, different voltages of at least 3 levels or more to the gate of a switching MOS transistor of said memory cells, a bias charge supplying means as said data reading circuit and a column register providing at least two or more storage cells which temporarily store said data.

Claims

1. A semiconductor memory having multiple level storage structure at least comprising a memory array including a plurality of memory cells respectively having at least one storage capacitor, an address selecting means which designates location of each memory cell, data lines which transfer data through connections to said memory cells and data writing and reading means being connected to said data lines, said memory further comprising

a means for sequentially applying, on time series basis, different voltages of at least three levels or more to said memory cells,

at least a data judging means, a first transfer gate provided between said judging means and data lines and a bias charge supplying means provided between said first transfer gate and the judging means, as said data reading means, and

a column register providing at least two or more storage cells which temporarily store said judged data.

2. A semiconductor memory having multiple level storage structure according to claim 1, wherein the bias charge supplying means comprises a precharge gate which is connected to the capacitor and the node between said capacitor and data judging means and a means which gives a pulse for supplying charges under the capacitor temporarily to the data lines and thereafter returns such charges.

3. A semiconductor memory having multiple level storage structure according to claim 2 wherein a second transfer gate is provided between the capacitor and data judging means which form the bias charge supplying means.

4. A semiconductor memory having multiple level storage structure according to claim 2 wherein a capacitor which forms the bias charge supplying means is formed by a depletion type MISFET.

5. A semiconductor memory having multiple level storage structure according to claim 2 wherein a capacitor which forms the bias charge supplying means is composed of an electrode formed on an insulating film and a high concentration semiconductor region formed under said insulating film.

6. A semiconductor memory having multiple level storage structure according to claim 2 wherein a capacitor which forms the bias charge supplying means is composed of an electrode, an insulating film and a semiconductor formed by the same process required for configuring the memory cells.

7. A semiconductor memory having multiple level strorage structure according to claim 1 wherein the memory cell array is located on the intersecting points of row address lines (word lines) and the data lines crossing thereto, the memory cells are composed of storage capacitors and the word gates which connect between the storage capacitors and data lines and are controlled by the voltage applied to the word lines, and a means for sequentially applying the time series voltages of at least three levels or more to the word gates is also provided.

8. A semiconductor memory having multiple level storage structure according to claim 1 wherein a column register is provided for each judging means, said column registers are started in such a timing that the charges which become data source discharge to the data lines by the time series voltages of three levels or more to be applied to the memory cells, and a means for temporarily storing the digital binary data generated in synchronization with said time series voltages or its decoded data to said column registers is also provided.

9. A semiconductor memory having multiple level storage structure according to claim 1 wherein, provided as the data writing means is a means which at least provides reset gates and writing gates connected to the data lines, extracts charge carrier by starting the writing gate in such a timing corresponding to the write data being synchronized with the time series voltages of three levels or more to be applied to the memory cells after the memory cells are filled with charge carriers by the reset gates, and writes multiple level data by retaining the charges which carry data of three levels or more corresponding to the time series voltages within the memory cells.

10. A semiconductor memory having multiple level storage structure according to claim 9 wherein a means which gives a timing pulse to the writing gate by referring to the data stored in the column register by the reading operation prior to the writing operation is provided as the refresh means.

11. A semiconductor memory having multiple level storage structure according to claim 1 wherein a reference cell (dummay cell) which reads charges of about 1/2 of signal charges per level in the memory cell and supplies it for each judgment is provided and a means which compares said signal charges with charges sent from dummy cells for judgment is provided as the data judging means.

12. A semiconductor memory having multiple level storage structure according to claim 11, comprising a row address select means where the data lines for reading signal charges sent from the memory cells and the data lines for reading reference charges sent from the dummy cell are provided in parallel, the memory cells and dummy cells are disposed so that when the one transmits signal charges, the other respectively transmits the reference charges, and selection of memory cells and dummy cells is also carried out corresponding thereto.

13. A semiconductor memory having multiple level storage structure according to claim 11 further comprising, as the data judging means, a flip-flop type judging means where two equivalent input terminals are provided so that the signal charges sent from the memory cells and reference charges sent from the dummy cells are input thereto respectively, the drains of at least a pair of MISFET'"'"'s are respectively connected to said input terminals, and said input terminals are also connected to the gates in the opposite sides.

14. A semiconductor memory having multiple level storage structure according to claim 11 further comprising, as a data judging means, the seven pairs of MISFET'"'"'s where two equivalent input terminals to which the signal charges sent from the memory cells and the reference charges sent from the dummy cells are applied are provided, these are respectively connected to the input gates and the sources are connected in common, a current supplying means connected to said common source, a pair of loads respectively connected to the drains of MISFET'"'"'s and a switch gate which short-circuits the input gates and drain terminals of said MISFET'"'"'s.

15. A semiconductor memory having multiple level storage structure according to claim 1 further comprising, as the data judging means, an amplifier having a MISFET for amplification where the input terminal to which the signal charges sent from the memory cells are input is connected to the gate while the drain is connected to the output terminal respectively and when said gate and drain are short-circuited the operating point is set to the sub-threshold region, a first switch means which connects the gate or drain of said MISFET to the power supply, a second switch means which short-circuits or opens the gate and drain of said MISFET and a third switch means which controls a current flowing into said MISFET.

16. A semiconductor memory having multiple level storage structure according to claim 1 further comprising a circuit for decoding the input digital binary data into multiple level data and a means which sequentially extracts said decoded multiple level data and sends it to the writing means in synchronization with the time series voltages of three levels or more to be applied to the memory cells during the writing operation.

17. A semiconductor memory having multiple level storage structure according to claim 1 wherein a column register is composed of storage cells storing only the binary data, at least N-1 or more storage cells are provided for each judging means when a number of multiple levels is N, a means for directly storing the multiple level data sent from memory cells of array is provided, and comprising an encoder having a second column register which sequentially sends such multiple level data and stores it, a means for simultaneously sending the data of a second column register to the encoding circuit and an encoding circuit which converts the multiple level data into the binary data.

18. A semiconductor memory having multiple level storage structure according to claim 1 further comprising a triggering pulse generator of variable frequencies having pseudo memory cells comprised of an electrode, an insulating film and a semiconductor formed by the same process as that required for configuring a capacitor for forming memory cells and a means which senses the discharge period of said pseudo memory cells and controls the oscillation frequency.

19. A semiconductor memory having multiple level storage structure according to claim 1 wherein the memory cell array is located at the intersecting points of the first row address lines, the second row address lines (plate lines) which are paired to said first row address lines (word lines) and provided in parallel thereto and the data lines crossing these lines, the memory cells are formed by the storage capacitors and the word gates provided between said storage capacitors and data lines, the gate electrode of a word gate is connected to the word lines and an electrode of the storage capacitor is connected to the plate lines, a means for sequentially applying the time series voltages of at least three levels or more to the plate line of selected row address and a means which makes conductive, with the voltage applied to said plate lines, the word gate of a row address selected by a voltage which is lower when electrons are signal charges or higher when holes are than the voltage to be applied to the storage capacitors are provided, at least the reset gate and write gate where the one terminal is respectively connected to the data lines are provided as the writing means, another terminal of the reset gate is connected, when the word gate is conductive, to a means which gives a voltage lower or higher than the channel voltage under the gate when electrons are signal charges or holes are, and the other terminal of a writing gate is connected, when the word gate is conductive, to a voltage which is higher or lower than the channel voltage under the gate when the electron is signal charges or hole are.

20. A semiconductor memory having multiple level storage structure according to claim 1 wherein said column register which writes digital data corresponding to the timing of voltage change of input signal into the first group of storage cells and reads the data being stored in said first group of storage cells as the write signal to said semiconductor memory having multiple level storage structure, hence disposing a plurality of columns of a ssecond group of storage cells incorporated to said first group of storage cells and comprising a first means for writing the digital data corresponding to the timing of voltage change of said input signal to said second group of storage cells, a second means which reads data in parallel from the second group of storage cells of the selected columns and a third means which writes data in parallel to said first group of storage cells on the selected columns.

21. A semiconductor memory having multiple level storage structure according to claim 1 wherein said second group of storage cells has the cells as many as the minimum integer m of log₂ n or more when a number of levels of said semiconductor memory having multiple level of storage structure is n.

22. A semiconductor memory having multiple level storage structure according to claim 2 wherein said first means supplies the m-bit code corresponding to the timing of voltage change of input signal to the writing control line group connected to the second group of storage cells and also writes thereto the digital data corresponding to the timing of voltage change of an input signal.

23. A semiconductor memory having multiple level storage structure according to claim 20 wherein said second means controls a voltage of a reading control line group connected to said second group of storage cells with the data stored in said second group of storage cells of selected columns.

24. A semiconductor memory having multiple level storage structure according to claim 3 or 4 wherein the writing control line group and reading control line group are used in common for said first and second means.

25. A semiconductor memory having multiple level storage structure according to claim 1 wherein said third means supplies the data to be written from the writing control line group connected to said first group of storage cells of each column.

26. A semiconductor memory having multiple level storage structure according to claim 1 wherein said second means and third means execute simultaneously the reading of data stored to said second group of storage cells and the writing of data to said first group of storage cells.

27. A semiconductor memory having multiple level storage structure according to claim 1 comprising, for fault toleration, a counter which executes counting in synchronization with the clock pulse, a ROM for storing location of defective memory cells or memory cell group, a comparator which compares an output of said counter and content of said ROM and a switching circuit which switches the regular memory cell or memory cell group or spare memory cell or memory cell group in accordance with an output of said comparator.

28. A semiconductor memory having multiple level storage structure according to claim 27 wherein said memory array is formed by providing memory cells at the intersecting points of a plurality of word lines and a plurality of data lines and comprises a means for serially reading or writing data of a part or all of the memory cells on the selected word lines in synchronization with the clock pulse, said ROM is used for storing location of data lines including defective memory cells or memory cell group, and said switching circuit is used for switching the regular data lines and spare data lines.