Memory access modes for a video display generator

• US 4,663,619 A
• Filed: 04/08/1985
• Issued: 05/05/1987
• Est. Priority Date: 04/08/1985
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Clarke, Charles J. Jr., Staggs, Kevin P.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/721,021
• Time in Patent Office: 757 Days
• Field of Search: 340/735, 340/744, 340/747, 340/748, 340/750, 340/703, 340/798, 340/799
• US Class Current: 345/567
• CPC Class Codes: G09G 5/026 Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A display memory which stores information to be displayed on a raster scan CRT comprises a first storage element for storing dot information, a second storage element for storing behavior information, and a third storage element for storing characteristic information. The first, second, and third storage element are each arranged in an nxm plane where m is an addressable location and each addressable location within each plane has n bits of information. Further, each of the first, second, and third storage elements has address terminals each operatively connected to a display address bus adapted to receive address information from a CPU.

Control logic receives address signals, data signals, and control signals from the CPU. The control logic generates enable control signals to selectively enable access to predetermined combinations of said first, second, and third storage elements in response to the address, data, and control signals from the CPU.

Claims

1. In a data processing system, having a display system, the display system which includes a central processing unit (CPU) producing data, address and control binary signals, and a display memory for storing binary signals representing information to be displayed, said display memory comprising:

(a) first random access storage means for storing binary dot information;

(b) second random access storage means for storing binary behavior information;

(c) third random access storage means, operatively connected to said first storage means, for storing binary characteristic information, said first, second, and third storage means each having "m" addressable storage locations with each addressable storage location storing "n" bits, where "m" and "n" are integers other than zero, each of said first, second, and third storage means having address terminals operatively connected to a display address bus for receiving concurrently binary address signals representing the addressable storage location from said CPU; and

(d) control logic means, having input terminals for receiving selected address signals, data signals, and control signals from said CPU, said control logic means being operatively connected to said first, second and third storage means for generating chip enable control signals said chip enable signals having a predetermined value enabling the storage means to store data signals produced by the CPU in an addressed memory location of the enabled first, second, or third storage means, the chip enable signals having said predetermined value being determined by the address, data, and control signals produced by said CPU and applied to said control logic means.

2. A display memory, according to claim 1, wherein said control logic means produces "n" unit enable control signals at "n" write enable output terminals respectively, each of said first, second, and third storage means having "n" write enable input terminals for receiving a write enable signal, each write enable terminal corresponding to a predetermined bit position within each of the "m" addressable locations of the associated storage means, each write enable terminal of said first storage means being operatively connected to a corresponding write enable terminal of said third storage means and to a corresponding write enable output terminal of said control logic means, said write enable signals having a predetermined value causing the addressed location of an enabled storage means to store a corresponding data signal produced by the CPU.

3. A display memory, according to claim 1, wherein said control logic means further comprises:

(a) decoder means for receiving control and address signals from said CPU, for decoding said signals, and for generating chip enable control signals and latch enable signals; and

(b) switch means, operatively connected to said CPU to receive data and decoded data signals and for producing "n" write enable signals at "n" write enable output terminals, said "n" write enable output terminals being operatively connected to "n" write enable terminals of said first and third storage means for determining which bit position of an addressed memory location data signals produced by the CPU are to be written.

4. A display memory, according to claim 3, wherein said second storage means has a write enable terminal for each bit position of an addressable storage location, the write enable terminals of the second storage means being operatively connected to a read/write control terminal of said CPU.

5. A display memory, according to claim 4, wherein said second storage means comprises:

first latch means having input terminals for receiving data signals from the CPU, said first latch means being operatively connected to data input terminals of the second storage means, said second storage means storing data signals from the CPU in response to predetermined one of the chip enable control signals and a latch enable signal applied to said first latch means, whereby said first storage means and said second storage means may have the same data written into addressable storage locations of the first and second storage means having the same address at the same time.

6. A display memory, according to claim 5, wherein said third storage means comprises:

(a) "p" memory planes where "p" is an integer greater than zero, each memory plane having "m" addressable locations and each location storing "n" data bits, each memory plane having a data input terminal corresponding to each of the "n" bits of data stored at each addressable location; and

(b) second latch means having "p" stages, each stage of said second latch means having an input terminal adapted to receive a data signal from the CPU, and having a corresponding output terminal operatively connected to each data input terminal of the "p" memory planes of the third memory means for storing data signals from said CPU in response to predetermined chip enable, write enable and latch enable control signals being produced by the control logic.

7. In a data processing system, having a display system having a raster scan CRT having pixels, the display system which includes a central processing unit (CPU) producing data, address, and control, signals and a display memory for storing binary signals determining the color and intensity of the pixels of the CRT as they are scanned, said display memory comprising:

(a) first random access storage means for storing dot information as binary signals;

(b) second random access storage means for storing behavior information as binary signals;

(c) third random access storage means operatively connected to said first storage means for storing characteristic information as binary signals, said first, second and third storage means having at least one memory plane with each memory plane having "m" addressable data storage locations with each storage location storing "n" data bits, where "m" and "n" are integers other than zero, each bit stored in each addressable location of said third storage means when utilized determining the display of a pixel having the same address and wherein all "n" bits of the corresponding "m" addressable locations of said first and second storage means determine the display of "n" pixels having the same address when utilized and determining whether the signals from the third, or first and second storage means have priority for display and further wherein each of said first, second and third storage means has address terminals each operatively connected to a display address for receiving address signals produced by said CPU; and

(d) control logic means, having input terminals for receiving address signals, data signals, and control signals from the CPU, said control logic means operatively connected to said first, second, and third storage means, for generating chip enable control signals to selectively enable data to be written into addressed storage locations of predetermined combinations of said first, second, and third storage means responsive to predetermined values of the address, data and control signals produced by the CPU.

8. A display memory, according to claim 7, wherein said control logic means produces "n" write enable control signals at "n" write enable output terminals respectively, each of said first, second and third storage means having "n" write enable input terminals, each write enable terminal corresponding to a predetermined bit position of each addressable storage location, each write enable input terminal of said first storage means being operatively connected to a corresponding write enable input terminal of said third storage means, and to a corresponding write enable output terminal of the control logic means for controlling which data bits are to be written into the first and third storage means during each write operation.

9. A display memory, according to claim 8, wherein said control logic means comprises:

(a) decoder means for receiving control and address signals from the CPU, for decoding said signals to generate chip enable control signals, latch enable control signals and multiplexer select signals; and

(b) switch means, operatively connected to the CPU for receiving selected input data signals and decoded data signals and for producing the "n" write enable signals at the "n" write enable output terminals.

10. A display memory, according to claim 9, wherein each write enable terminal of said second storage means is operatively connected to said CPU to receive a read/write control signal produced by the CPU when writing data into said display memory.

11. A display memory, according to claim 10, wherein said second storage means further comprises:

(a) "n" data input terminals; and

(b) first latch means, said first latch means having "n" input terminals adapted to receive "n" data signals from said CPU, said first latch means being operatively connected to said data input terminals of said second storage means, said second storage means storing said data signals from the first latch means in response to a predetermined one of said chip enable memory control signals and a latch control signal being produced by the control logic means whereby said first and second storage means may have the same data written into memory locations having the same address simultaneously.

12. A display memory, according to claim 11, wherein said third storage means comprises:

(a) "p" planes, where "p" is an integer greater than zero, each memory plane having a data input terminal; and

(b) second latch means, having "p" stages, each stage of said second latch means having an input terminal for receiving a data signal from the CPU and having a corresponding output terminal operatively connected to the data input terminal of the corresponding memory plane of the third storage means, each memory plane when enabled by a chip enable signal storing a data signal in an addressed storage location determined by the address signals produced by the CPU in a bit position determined by a write enable signal produced by the control logic.