Decoding arrangements for synchronous receivers

• US 4,663,623 A
• Filed: 08/03/1984
• Issued: 05/05/1987
• Est. Priority Date: 08/03/1983
• Status: Expired due to Fees

• Current Assignee: Multitone Electronics PLC (Kantone Holdings Ltd.)
• Original Assignee: Multitone Electronics PLC (Kantone Holdings Ltd.)
• Inventors: Barker, William R., Lax, Alexander P.
• Primary Examiner(s): YUSKO, DONALD
• Application Number:
  US06/637,439
• Time in Patent Office: 1,005 Days
• Field of Search: 340/825.44, 455/32, 455/343, 455/228
• US Class Current: 340/7.34
• CPC Class Codes: G08B 3/1066 with other provisions not elsewhere provided for, e.g. turn-off protection
• CPC Class Codes: H04W 88/026 using digital address codes

Abstract

In a decoder suitable for use in a paging receiver of the type responsive to a transmission which includes a preamble sequence followed by batches each containing a synchronization word followed by a plurality of address and/or message words, the decoder is operative to detect a single synchronization word. Thereafter, the decoder is powered up to search in its specific frame in each batch by means of a clock which has been synchronized with the transmission and which provides the timing for searching in the specific frame of all subsequent batches.

The clock may have coarse and fine modes of timing control, the coarse mode being applicable when initial bit synchronization is being attained, and the fine mode being applied subsequently to reduce the risk of the clock drifting out of synchronization.

Claims

1. In a decoding arrangement for decoding a transmission including batches of words, each batch comprising a respective synchronisation word followed by a plurality of code words, the arrangement comprising:

receiver means for receiving said transmission;

power control means for controlling supply of power to said receiver means;

transmission detection means operative to detect receipt of said transmission by said receiver means;

synchronisation word detection means operative to detect one of said synchronisation words;

address detection means operative to detect an address word included in one of said pluralities of code words; and

synchronisation-control means operative alternately to activate and deactivate said power control means respectively to enable and inhibit reception of said transmission by said receiver means so that reception is enabled at a predetermined time within each batch to allow said address detection means to detect said address word at said predetermined time;

the improvement wherein;

said synchronisation-control means includes a clock and is responsive to detection by said synchronisation word detection means of a single one of said synchronisation words to put said clock into word synchronisation with said transmission, and to inhibit said synchronisation word detection means from detecting any further synchronisation words in the same transmission;

said synchronisation-control means is operative to derive each of said predetermined times at which reception is enabled from the time at which said single synchronisation word was detected by said synchronisation word detection means; and

said synchronisation-control means is responsive to an indication by said transmission detection means that said transmission is no longer being received by said receiver means to put said decoding arrangement into a condition ready to receive another said transmission.

2. A decoding arrangement according to claim 1, wherein the synchronisation-control means includes timing correction means operative to apply a variable timing correction factor to the clock, the timing correction means being responsive to the transmission detection means detecting receipt of a transmission to reduce the correction factor applied to the clock.

3. A decoding arrangement according to claim 2, wherein the timing correction means is operative in first and second modes respectively applying different correction factors.

4. A decoding arrangement according to claim 2, wherein the transmitted batches of words include level transitions, and the timing correction means applies the correction factor once only per n level transitions, n being greater than one.

5. A decoding arrangement according to claim 1, wherein the transmission detection means comprises at least one preamble detector operative to detect a preamble sequence preceding the batches of words in the transmission.

6. A decoding arrangement according to claim 1, wherein the transmission detection means comprises a data detector operative to detect the code words in the transmission.

7. A decoding arrangement according to claim 6, wherein the code words comprise data bits and check bits, and the data detector comprises means operative to calculate expected check bits of the code words from the data bits thereof, and to compare the expected check bits with those in the received code words.

8. A decoding arrangement according to claim 7, wherein the means operative to calculate and to compare comprises means to effect a comparison between the expected and received check bits to produce a difference pattern and the transmitted code words have the property that the difference pattern produced is independent of the particular correct code word.

9. A decoding arrangement according to claim 1, comprising alert generating means responsive to detection by the address detection means to generate an alert in a pattern so that the alert is generated only when the power control means is inhibiting reception of the transmission, while still maintaining a regular pattern.

10. A decoding arrangement according to claim 1, wherein the transmission detection means comprises a preamble detector means and a data detector means, the data detector means being operative to detect the code words in the transmission, and in the absence of such detection the preamble detector means being operative to detect a preamble sequence preceding the batches of words in the transmission, the synchronisation word detection means being enabled to detect a subsequent synchronisation word if preamble has been detected by said preamble detector means.