Random/serial access mode selection circuit for a video memory system

• US 4,663,735 A
• Filed: 12/30/1983
• Issued: 05/05/1987
• Est. Priority Date: 12/30/1983
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Novak, Mark F., Guttag, Karl M.
• Primary Examiner(s): Williams, Archie E.
• Assistant Examiner(s): Munteanu, Florin
• Application Number:
  US06/567,111
• Time in Patent Office: 1,222 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/521, 365/219, 365/220, 365/221, 365/239, 365/230, 365/233, 365/189, 340/750, 340/798, 340/799, 340/800, 340/801
• US Class Current: 345/533
• CPC Class Codes: G09G 2360/123 using interleaving
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM

Abstract

In a video computer system, an improved memory circuit is provided which is effective for delivering stored data only at appropriate instances, and which is also simpler and more reliable in design. In particular, the system preferably includes a bit-mapped RAM circuit which assumes a serial mode in response to both a row address signal and a suitable data output control signal, and which assumes a parallel or "random" mode when only the row address is received. Stored data is transferred to a parallel output terminal in the RAM circuit, or to a serial output terminal therein, depending upon the sequence of these signals as well as the column address and read signals, whereby the data output control signal is used for two separate and different purposes within the system.

Claims

1. Apparatus for reading data stored in a random access memory array device, said memory array comprising a plurality of memory cells arranged in rows and columns, said device having a single-bit output and a serial multiple-bit output, comprising:

processor means for generating a data output control signal and a row address signal, and for applying said signals to said device, and

means in said device, responsive to said data output control signal and to said row address signal, for applying said stored data to said serial multiple-bit output responsive to said processor means applying said data output control signal to said device prior to applying said row address signal to said device, and for applying said stored data to said single-bit output of said device responsive to said processor means applying said data output control signal a predetermined time after applying said row address signal to said device.

2. The apparatus described in claim 1, wherein said processor means further generates a read signal, and applies said read signal to said memory array device;

and wherein said applying means in said device is further responsive to said read signal so that said stored data is applied to said single-bit output or to said serial multiple-bit output of said device only if said read signal is also applied to said device.

3. A computer system comprising:

(a) video display means having video signal input means for receiving bit-serial video data for display of data on a screen, said video singal input means connected to a video data path,

(b) bit-mapped video memory means including at least one video memory device, each said video memory device constructed in a single semiconductor integrated circuit and having both bit-serial and single-bit access ports, each said memory device comprising;

(i) an array of rows and columns of read/write memory cells,

(ii) addressing means for selecting rows, or selecting rows and columns, in response to address bits applied to address terminals of the device and in response to an address strobe applied to a control terminal of said device,

(iii) serial register means, and means for loading data from a row of said cells selected by said addressing means to said serial register means,

(iv) a serial data output terminal connected to said serial register means, said output terminal connected to said video data path and thereby coupled to said video signal input means,

(v) at least one single-bit data input terminal, and at least one single-bit data output terminal, and means connecting said at least one single-bit data input and data output terminals to a column or columns selected by said addressing means,

(vi) and control means receiving said address strobe and receiving a control signal from another terminal of said device, and selecting serial access responsive to receiving said control signal prior to said address strobe, and selecting single-bit access responsive to receiving said control signal a predetermined time after receiving said address strobe,

(c) and microprocessor means having bit-parallel bus means separate from said video data path, said bus means coupled to said bit-mapped video memory means, said microprocessor means applying addresses to said address terminals of said at least one video memory device via said bus means for selecting said rows for loading to said serial register means and for selecting rows and columns for said single-bit access, said microprocessor means applying data to said at least one data input terminal of the device via said bus means for writing into said memory cells, said data being supplied to said at least one single-bit data terminal during the time that at least some of the bit-serial video data is being applied to said video signal input means via said video data path, and said microprocessor means applying said address strobe and said control signal to said memory means.

4. A system according to claim 3 wherein said video memory means includes a plurality of said video memory devices, and all of said plurality of video memory devices receive addresses from said bus means in parallel,

and further comprising means for coupling the serial data output terminals of said plurality of video memory devices to said video data path.

5. A system according to claim 4 wherein said coupling means includes shift-register means receiving video data from said serial data output terminals of said plurality of video memory devices, and at least one serial data output from said shift register means is coupled to said video signal input means.

6. A system according to claim 5 including first means for clocking said shift register means, and second means for clocking said serial register means of said plurality of video memory devices.

7. A system according to claim 6 wherein said first means for clocking said shift register means has a clock rate much faster than said second means for clocking said serial register means.