Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers

• US 4,663,831 A
• Filed: 10/08/1985
• Issued: 05/12/1987
• Est. Priority Date: 10/08/1985
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Birrittella, Mark S., Reuss, Robert H., Liaw, Hang M.
• Primary Examiner(s): Saba, William G.
• Application Number:
  US06/785,640
• Time in Patent Office: 581 Days
• Field of Search: 148/174, 148/175, 148/DIG. 11, 148/DIG. 20, 148/DIG. 26, 148/DIG. 50, 148/DIG. 117, 148/DIG. 164, 29/576 E, 29/576 W, 357/34, 357/35, 357/50, 357/59, 357/71, 156/643, 156/653, 156/657
• US Class Current: 438/348
• CPC Class Codes: H01L 21/28531 Making of side-wall contacts
• CPC Class Codes: H01L 29/66287 with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation H01L29/6628 takes precedence
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: Y10S 148/011 Bipolar transistors
• CPC Class Codes: Y10S 148/02 Contacts, special
• CPC Class Codes: Y10S 148/026 Deposition thru hole in mask
• CPC Class Codes: Y10S 148/05 Etch and refill
• CPC Class Codes: Y10S 148/117 Oxidation, selective
• CPC Class Codes: Y10S 148/164 Three dimensional processing

Abstract

Improved bipolar transistors having minimum base-collector and collector-substrate junction area are formed by using multiple polycrystalline (e.g. doped poly silicon) layers to make lateral contact to a pillar shaped single crystal device region. The lateral poly silicon contacts are isolated from each other and the substrate and extend to the upper surface of the device for external connections. The structure is made by depositing two dielectric-poly layer sandwiches, etching and oxidizing part of the poly silicon layers to provide isolated overlapping poly silicon regions, etching a first hole through both poly silicon regions to the substrate, etching a second hole to the lower poly silicon layer, and filling the first and second holes with single and poly-crystalline silicon, respectfully. A sidewall oxide is formed at the periphery of the top of the single crystal pillar for defining the emitter location without additional masking.

Claims

1. A process for forming sidewall contact transistors comprising:

providing a substrate having on a portion thereof a first dielectric region covered by a first polycrystalline conductor region;

providing on said first polycrystalline conductor region a first etch and oxidation resistant mask covering a first portion thereof leaving exposed a second portion thereof;

etching away 30-60 percent of the thickness of said first polycrystalline conductor region in said second portion thereof;

oxidizing the remainder of said second portion of said polycrystalline conductor region to form a second dielectric region;

removing said first mask;

providing a second polycrystalline conductor region above and insulated from said first polycrystalline conductor region by a third dielectric region;

providing on said second polycrystalline region a second etch and oxidation resistant mask covering a first portion and leaving exposed a second portion thereof, and wherein said first portion of said second polycrystalline conductor region overlies some of said first portion of said first polycrystalline conductor region;

etching away 30-60 percent of the thickness of said second polycrystalline conductor region in said second portion thereof;

oxidizing the remainder of said second portion of said second polycrystalline conductor region to form a fourth dielectric region;

covering said first portion of said second polycrystalline conductor region by a fifth dielectric region having an outer surface;

removing first superposed parts of said first, third and fifth dielectric regions and said first and second polycrystalline conductor regions to expose a first part of said substrate underlying said first superposed parts;

removing second superposed parts of said third, fourth, and fifth dielectric regions to expose a second part of said first polycrystalline conductor region; and

forming a pillar of single crystal semiconductor material on said exposed first part of said substrate and a pillar of polycrystalline conductor material on said exposed second part of said first polycrystalline conductor region, wherein said single crystal pillar contacts said first portions of said first and second polycrystalline conductor regions and has an outer surface lying below said outer surface of said fifth dielectric region, and wherein said outer surface of said single crystal pillar and said outer surface of said fifth dielectric region form a step, and wherein said polycrystalline conductor pillar has an exposed surface.

2. The process of claim 1 further comprising:

covering said outer surface of said single crystal pillar, said exposed surface of said polycrystalline conductor pillar and said outer surface of said fifth dielectric region with a sixth dielectric region;

etching said sixth dielectric region to form a dielectric spacer at said step, wherein said dielectric spacer covers a peripheral portion and leaves exposed a central portion of said outer surface of said single crystal semiconductor pillar; and

doping a near surface part of said single crystal semiconductor pillar with a dopant of a first conductivity type.

3. The process of claim 2 further comprising, prior to said step of doping a near surface part of said single crystal semiconductor pillar with a dopant of a first conductivity type, doping the portion of said single crystal semiconductor pillar which contacts said first portion of said second polycrystalline conductor region with a dopant of a second conductivity type.

4. The process of claim 2 further comprising electrically contacting said first part of said second polycrystalline conductor region, said central portion of said surface of said single crystal region and said exposed surface of said polycrystalline pillar.

5. The process of claim 4 wherein said electrically contacting step comprises first exposing a first part of said first portion of said second polycrystalline region after said step of removing second superposed parts of said third, forth, and fifth dielectric layers.

6. The process of claim 4 wherein said electrically contacting step comprises contacting with a third polycrystalline region.

7. The process of claim 6 wherein said electrically contacting step is performed prior to said step of doping said single crystal pillar with a dopant of said first type, and wherein the portion of said polycrystalline region above said central portion of said outer surface of said single crystal pillar is of said first conductivity type and acts as a diffusion source for said step of doping said single crystal pillar with said first conductivity type dopant.

8. A process for forming semiconductor devices comprising:

providing s single crystal substrate;

providing a first dielectric layer on said substrate;

providing a first oxidizable conductor layer on said first dielectric layer, having thereon a first oxidation resistant mask covering a first region thereof and exposing a second region thereof, and etching away 30-60 percent of the thickness of said second region thereof, leaving behind a first remainder, and oxidizing said first remainder to replace said second region with a first oxide;

providing a second dielectric layer above said first region of said first conductor;

providing a second oxidizable conductor layer at least on said second dielectric layer, having thereon a second oxidation resistant mask covering a first region thereof and exposing a second region thereof, and etching away 30-60 percent of the thickness of said second region thereof, leaving behind a second remainder, and oxidizing said second remainder to replace said second region with a second oxide;

wherein said first region of said second conductor layer has a first portion overlapping a first portion of said first region of said first conductor layer;

forming a first opening through at least part of said first portions of said first and second conductor regions penetrating to said substrate;

forming a second opening laterally separated from said second conductor region and penetrating to said first conductor region;

filling a portion of said first opening with single crystal semiconductor material which contacts both said first and second conductor regions in said first opening;

filling a portion of said second opening with polycrystalline material which contacts said first conductor region;

introducing a first dopant into an upper part of said single crystal semiconductor material to a first depth;

forming sidewall spacers at the lateral sides of said first opening and at the surface of said upper part of said single crystal semiconductor material and then introducing a second dopant into said upper part of said single crystal semiconductor material in a region between said sidewall spacers to a second depth less than said first depth; and

forming electrical connections to said single crystal semiconductor material, said conductor material in said second opening, and said second polycrystalline region.

9. The process of claim 8 wherein said second conductor region is covered by a dielectric masking layer having an outer surface and said first filling step comprises filling said first opening to a level below the level of said outer surface of said dielectric masking layer at said opening to create a surface height step between the outer surface of said single crystal semiconductor material and the outer surface of said dielectric masking layer, and wherein said process step of forming said sidewall oxide spacers comprises the process steps of conformally covering said outer surface of said dielectric masking layer and the outer surface of said single crystal semiconductor material with another dielectric masking layer having a first vertical thickness above said outer surface of said dielectric masking layer but greater vertical thickness at said surface height step, and then anisotropically removing said first thickness of said another dielectric masking layer.