Device for transmitting of binary data between a mobile data carrier and a stationary station

• US 4,665,399 A
• Filed: 09/19/1985
• Issued: 05/12/1987
• Est. Priority Date: 07/26/1984
• Status: Expired due to Fees

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: List, Hans, Fauser, Edwin, Schirmer, Gunter
• Primary Examiner(s): Myracle, Jerry M.
• Application Number:
  US06/783,226
• Time in Patent Office: 600 Days
• Field of Search: 340/870.31, 340/825.71, 340/870.32, 340/531, 340/679, 340/680, 336/30
• US Class Current: 340/870.32
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: G07C 9/28 the pass enabling tracking or indicating presence
• CPC Class Codes: H04B 5/00 Near-field transmission systems, e.g. inductive or capacitive transmission systems
• CPC Class Codes: H04B 5/22 Capacitive coupling
• CPC Class Codes: H04B 5/266 One coil at each side, e.g. with primary and secondary coils

Abstract

A device for transmitting of binary data between a mobile data carrier (10) and a stationary station (11) is provided with a first resonance circuit (13) in the stationary station (11), whereby a switchable field effect transistor (25) is parallel switched to its condenser (17) by means of a switching pulse sequence, a second resonance circuit (12) in the data carrier (10) which is at least conductively coupled for a short time with the first resonance circuit (13). For the purpose of enlarging the inductively to be bridged distances between the resonance circuits (12,13) of data carrier (10) and stationary station (11) without impairing the operating safety during the data transmission the resonance circuit (13) in the stationary station (11) is designed in such a manner that its resonance frequency is about equal to the switching pulse sequence. The data transmission from the data carrier (10) to the stationary station (11) is performed by amplitude demodulation in the data carrier (10) and by amplitude demodulation in the stationary station (11). The data transmission from the stationary station (11) to the data carrier (10) is performed by frequency demodulation, whereby the frequency ratio is adjusted to 2:1.

Claims

1. A device for transmitting binary data between a mobile data carrier (10) and a stationary station (11), the data carrier (10) having a passing movement past the stationary station (11), in particular between a workpiece support and one of a finishing station and a control station on one of transfer conveyors and assembly conveyors, the device comprising:

means for transmitting binary data between a mobile data carrier (10) and a stationary station (11) and including a first resonance circuit (13) associable with the stationary station and having a capacitor (17), a first coil (16) and a first resonance frequency, and a second resonance circuit (12) associable with the data carrier and having a second coil (14) inductively coupled, at least for a short time, with said first coil (16) during a passing movement of the data carrier past the stationary station, said second resonance circuit (12) having a resonance with an amplitude when said second coil (14) is inductively coupled with said first coil (16);

means for providing at least one switch pulse sequence with a frequency and including a first electronic switch (25) connected in parallel to said capacitor (17) of said first resonance circuit (13);

means for influencing said resonance in dependency upon one of two binary values of data to be transmitted by the data carrier to the stationary station and including a modulation circuit (28) connected with said second resonance circuit (12); and

means for recovering a binary value when transmitted and including a demodulation circuit (37) connected with said first resonance circuit (13), said first resonance circuit (13) being formed so that said first resonance frequency is about equal to said frequency of said switch pulse sequence, said influencing means being formed to modulate said amplitude of said resonance, and said recovering means being formed to recover the binary value in said first resonance circuit (13) by amplitude demodulation of said resonance.

2. A device as defined in claim 1, wherein said first electronic switch (25) is formed as a transistor.

3. A device as defined in claim 1, wherein said providing means is formed so that said switch pulse sequence has a frequency halvable in dependency on one of two binary values of the data to be transmitted from the stationary station to the data carrier.

4. A device as defined in claim 1, wherein said modulation circuit (28) is formed such that an amplitude modulation of said second resonance circuit (12) is substantially performable only in a negative semiwave of said second resonance circuit (12).

5. A device as defined in claim 1, wherein said modulation circuit (28) has a further coil (30), said transmitting means further including a ferrite core (18) on which said second coil (14) and said further coil (30) are disposed, a second electronic switch (32) having a control input side, an AND-gate (33) with a first input side and a second input side and an output side, said first input side being formed so that the data to be transmitted from the data carrier is applicable to said first input side of said AND-gate, said output side being being connected to said control input side of said second electronic switch (32), a diode (21), and a monoflop (34) having an input side connected to said second resonance circuit (12) and an output side connected to said second input side of said AND-gate (33), said second electronic switch (32) being connected in series with said further coil (30) and in parallel with said diode (21).

6. A device as defined in claim 5, wherein said second electronic switch (32) is formed as a field effect transistor.

7. A device as defined in claim 5, wherein said modulation circuit (28) further includes a synchronization latch (35) formed as a D-flip-flop located upstream of said first input side of said AND-gate (33) and having a D-input side, said D-input side being formed so that the data to be transmitted is appliable in an inverted manner to said D-input side, said synchronization latch (35) also having a cycle input side connected with said output side of said monoflop (34).

8. A device as defined in claim 7, wherein said providing means includes a plurality of said switch pulse sequences, each of said switch pulse sequences having a transmitting degree associated with each binary value that is equally uniform.

9. A device as defined in claim 1, wherein said first electronic switch (25) has a control input terminal;

further comprising;

means for generating said switch pulse sequence including a rectangular-wave generator (26) having an output port connected to said control input terminal of said first electronic switch (25) in said first resonance circuit (13), and including a frequency modulator (27) formed so that said frequency of said switch pulse sequence is halved and a duration of said switch pulse sequence is doubled when applying one of two binary values of the data to be transmitted to the data carrier (10).

10. A device as defined in claim 9, further comprising:

means for applying binary values to said frequency modulator (27) and including a synchronization latch (50), said frequency modulator (27) having an output port, said synchronization latch (50) being formed as a D-flip-flop having a cycle input connected to said output port of said frequency modulator (27) and having a D-input port formed so that the binary values are immediately available.

11. The device as defined in claim 10, wherein said recovering means includes a synchronization latch (50) with an output connected to said second input side of said NAND-gate (40).

12. The device as defined in claim 1, wherein said second resonance circuit has an output, said recovering means including a further demodulation circuit (53) for recovering data transmitted from the stationary station (11) to the data carrier (10) and being connected to said second resonance circuit (12), said further demodulation circuit (53) including a first monoflop (34) having an input connected to said output of said second resonance circuit (12) and having an output, a pulse filter (55) having an input connected to said output of said first monoflop (34) and an output, a second monoflop (56) having an input connected to said output of said pulse filter (55) and having an output, and a D-flip-flop (57) having a D-input connected to said output of said second monoflop and having a cycle input connected to said output of said pulse filter (55) and having an output formed so that transmitted data can be removed therefrom.

13. A device as defined in claim 12, wherein said modulation circuit (28) also includes said first monoflop (34).

14. A device as defined in claim 1, further comprising:

a direct voltage supply (20), said demodulation circuit (37) including a peak rectifier (38) effective in a negative semiwave of said resonance, a NAND-gate (40) and having a first and second input side and an output side, a third electronic switch (39) connected to said direct voltage supply (20) and said NAND-gate (40), said peak rectifier (38) having an output connected to said third electronic switch (39), a high pass filter (44,

     45) connecting said third electronic switch (39) to said direct voltage supply (20), and a low pass filter (48,

     49) connecting said first input side of said NAND-gate (40), said second input side of said NAND-gate (40) being formed so that a synchronization bit is appliable thereon, said output side of said NAND-gate (40) being connected to said control input side of said third electronic switch (39).

15. A device as defined in claim 14, wherein said NAND-gate (40) has a Schmitt-trigger input.

16. The device as defined in claim 14, wherein said recovering means includes a synchronization latch (50) with an output connected to said second input side of said NAND-gate (40).

17. A device as defined in claim 14, wherein said electronic switch (39) in formed as a npn-transistor, said second input side of said NAND-gate (40) being formed such that said synchronization bit appliable thereon is provided with a binary value logic of "1".

18. The device as defined in claim 17, wherein said recovering means includes a synchronization latch (50) with an output connected to said second input side of said NAND-gate (40).