Non-volatile dynamic random access memory cell

• US 4,665,417 A
• Filed: 04/23/1986
• Issued: 05/12/1987
• Est. Priority Date: 09/27/1984
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lam, Chung H.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/856,443
• Time in Patent Office: 384 Days
• Field of Search: 357/23.5, 357/23.6, 365/149, 365/184, 365/185
• US Class Current: 257/298
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: H01L 29/7882 charging by injection of carriers through a conductive insulator, e.g. Poole-Frankel conduction

Abstract

A non-volatile dynamic memory cell in which the non-volatile element has two different areas for electron injection, such that direct overwriting of previously stored non-volatile data is permitted without an intervening erase cycle. The non-volatile storage element is a floating gate electrode which has dual control gates disposed thereon. Each control gate includes a layer of dual electron injector structure (DEIS) and a polysilicon gate. When writing a "0" from the volatile storage capacitor to the floating gate, one of the programming gates removes charge from the floating gate. To write a "1", the other programming gate injects charge into the floating gate. The above charge transfer does not take place if the previously stored logic gate and the logic state to be written in are identical.

Claims

1. A non-volatile dynamic memory cell, comprising:

a semiconductor substrate of a first conductivity type having a first surface portion which functions as a dynamic storage node for storing first and second logic states a first surface region of a second conductivity type, and a second surface portion disposed between said first surface portion and said first surface region;

a transfer device for selectively coupling data signals between said first surface portion and said first surface region;

a floating gate electrode disposed on and insulated from said second surface portion said substrate;

first and second charge injection means disposed on said floating gate electrode for injecting charge into and removing charge from respectively, said floating gate electrode, each of said first and second charge injection means comprising a layer of silicon oxide having excess silicon crystals on its upper and lower surfaces; and

first and second control electrodes disposed on said first and second charge injection means, respectively, said first and second control electrodes receiving first and second control signals, respectively, for initiating said charge transfer by said first and second charge injection means, respectively, such that said first charge injection means removes charge from said floating gate electrode when said first logic state is to be stored by said floating gate electrode and said second charge injection means injects charge into said floating gate electrode when said second logic state is to be stored by said floating gate electrode, as a function of the voltage on said first surface portion as well as the charge previously stored by said floating gate electrode, to overwrite said first and second logic states into said floating gate electrode.

2. The memory cell as recited in claim 1, wherein said first surface region comprises a diffused bit line.

3. The memory cell as recited in claim 1, wherein said transfer device comprises a word line device having a gate electrode insulated from and overlaying said semiconductor substrate, said diffused bit line comprising a drain electrode of said word line device.

4. The memory cell as recited in claim 1, wherein said floating gate electrode is comprised of a first layer of polycrystalline silicon, and wherein said first and second control electrodes are comprised of a second layer of polycrystalline silicon.

5. The memory cell is recited in claim 3, wherein said gate electrode of said word line device is comprised of said second layer of polycrystalline silicon.

6. The memory cell as recited in claim 1, wherein each of said first and second charge injection means initiate charge transfer when a differential voltage of greater than +10 volts or less than -10 volts is applied thereto.

7. The memory cell as recited in claim 1, wherein each of said first and second charge injection means comprises a layer of silicon oxide having excess silicon crystals on its upper and lower surfaces.

8. The memory cell as recited in claim 1, further comprising a storage plate electrode disposed on and insulated from said dynamic storage node.

9. The memory cell as recited in claim 8, wherein said storage plate electrode and one of said first and second control electrodes are electrically in common.

10. A memory cell for storing data in volatile and non-volatile forms, the non-volatile storage having an overwrite capability, comprising:

a semiconductor substrate of a first conductivity type having a first surface portion which comprises a dynamic storage node for storing first and second logic states, a first surface region of a second conductivity type which comprises a diffused bit line, and a second surface portion disposed between said first surface portion and said first surface region;

a transfer device having a gate electrode disposed on and insulated from said semiconductor substrate, said transfer device selectively coupling data signals between said first surface portion and said first surface region to control the logic state stored by said first surface portion;

a non-volatile storage means disposed on and insulated from said second surface portion; and

first and second control gates disposed on said non-volatile storage means and receiving first and second control signals, respectively, each of said first and second control gates comprising a layer of silicon oxide having excess silicon crystals on its upper and lower surfaces overlaid by a layer of conductive material, said first control gate removing charge from said non-volatile storage means when said first surface portion of said substrate is storing a first voltage indicative of said first logic state, and said second control gate injecting charge into said non-volatile storage means when said first region of said substrate is storing a second voltage indicative of said second logic state, said charge injection or charge removal also being a function of the charge previously stored by said non-volatile storage means so that said logic states are overwritten from said dynamic storage node into said non-volatile storage means.

11. The memory cell as recited in claim 10, further comprising a storage plate electrode disposed on and insulated from said dynamic storage node.

12. The memory cell as recited in claim 11, wherein each of said first and second control gates comprises a layer of charge injector material formed on said non-volatile storage means and a layer of polysilicon overlaying said charge injector material.

13. The memory cell as recited in claim 12, wherein said layer of charge injector material comprises a layer of silicon oxide having excess silicon crystals on its upper and lower surfaces.

14. A semiconductor memory cell formed on a semiconductor substrate, the cell being capable of storing data in non-volatile and dynamic forms, comprising:

a transfer device for selectively coupling data signals between a data line and a dynamic storage node on the surface of a semiconductor substrate;

a floating gate electrode insulated from and overlying a portion of said semiconductor substrate between said transfer device and said dynamic storage node;

first and second charge injection means overlying first and second regions of said floating gate electrode for injecting charge into and removing charge from, respectively, said floating gate electrode, each of said first and second charge injection means comprising a layer of silicon oxide having excess silicon crystals on its upper and lower surfaces;

first and second control electrodes disposed on said first and second charge injection means, respectively, for writing new data from said dynamic storage node into said floating gate electrode by initiating charge transfer between one or the other of said first and second charge injection means and said floating gate electrode in response to (a) independent control signals received by said first and second control electrodes, respectively, and (b) the previously stored charge on said floating gate electrode, said new data being overwritten into said floating gate electrode.

15. The memory cell as recited in claim 14, wherein said data line comprises a diffused bit line and said transfer device comprises a word line device, said diffused bit line comprising a drain electrode of said word line device.

16. The memory cell as recited in claim 14, wherein said first control electrode further comprises a storage capacitor plate insulated from and overlaying said dynamic storage node.

17. The memory cell as recited in claim 14 wherein said layer of charge injector material comprises a layer of silicon oxide having excess silicon crystals on its upper and lower surfaces.

18. A semiconductor memory cell capable of storing binary data in volatile and non-volatile forms, comprising:

a storage capacitor comprising a semiconductor substrate having a dynamic storage node for storing first and second binary logic states on a surface thereof and a storage capacitor plate formed above and insulated from said dynamic storage node;

a word line device formed on said surface of said semiconductor substrate for coupling data signals between a data line formed on said surface of said substrate and said dynamic storage node;

a floating gate electrode formed on and insulated from a portion of said surface of said semiconductor substrate between said storage capacitor and said word line device;

first and second charge injection means formed on separate regions of said floating gate electrode, said first and second charge injection means being capable of injecting charge into and removing charge from said floating gate electrode, each of said first and second charge injection means comprising a layer of silicon oxide having excess silicon crystals on its upper and lower surfaces; and

first and second control electrodes disposed on said first and second charge injection means, respectively, said first and second control electrodes receiving first and second control signals, respectively, such that said first charge injection means removes charge from said floating gate electrode when a first binary logic state is to be stored by said floating gate electrode and said second charge injection means injects charge into said floating gate electrode when a second logic state is to be stored by said floating gate electrode, said charge removal or charge injection also being a function of the binary logic state currently stored by said floating gate electrode, such that said binary logic states may be overwritten into said floating gate electrode.

19. The memory cell as recited in claim 18, wherein each of said first and second charge injection means initiate charge transfer when a differential voltage of greater than +10 volts or less than -10 volts is applied thereto.

20. A memory cell storing logic data in volatile and non-volatile forms, the non-volatile storage having an overwrite capability, comprising:

a storage capacitor comprising a semiconductor substrate having a dynamic storage node on a surface thereof and a storage capacitor plate formed above and insulated from said dynamic storage node;

a transfer device formed on said surface of said semiconductor substrate, said transfer device having a drain electrode comprising a diffused bit line, said transfer device selectively coupling data signals between said diffused bit line and said dynamic storage node;

a floating gate electrode formed above and insulated from a portion of said semiconductor substrate between said transfer device and said storage capacitor;

first and second charge injection means formed on separate regions of said floating gate electrode, said first and second charge injection means being capable of injecting charge into and removing charge from, respectively, said floating gate electrode, each of said first and second charge injection means comprising a layer of silicon oxide having excess silicon crystals on its upper and lower surfaces; and

first and second control electrodes disposed on said first and second charge injector means, respectively, said second charge injector means, respectively, said second control electrode being electrically in common with said storage capacitor plate, said first and second control electrodes receiving independent control voltages such that either one of said charge injection means injects charge into said floating gate electrode or the other of said charge injection means removes charge from said floating gate electrode, as a function of a pre-existing charge on said floating gate electrode and the logic state of said dynamic storage node, whereby said first and second charge injector means are prohibited from performing either said charge injection or said charge removal when the logic state to be stored by said floating gate electrode is the same as the logic state currently stored thereon.