Method of making a semiconductor transducer having multiple level diaphragm structure

• US 4,665,610 A
• Filed: 04/22/1985
• Issued: 05/19/1987
• Est. Priority Date: 04/22/1985
• Status: Expired due to Fees

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford University)
• Original Assignee: Stanford University
• Inventors: Barth, Phillip W.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): McAndrews, Kevin
• Application Number:
  US06/725,984
• Time in Patent Office: 757 Days
• Field of Search: 357/26, 29/576 C, 29/576 E, 29/580, 156/647, 156/653, 156/644, 148/DIG. 50, 148/DIG. 26, 148/DIG. 159
• US Class Current: 438/53
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2203/0118 Cantilevers
• CPC Class Codes: B81B 2203/0361 Tips, pillars
• CPC Class Codes: B81C 1/00158 Diaphragms, membranes manufacture process for semi-permeable inorganic membranes B01D67/0039
• CPC Class Codes: B81C 2201/0197 Processes for making multi-layered devices not provided for in groups B81C2201/0176 - B81C2201/0192
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm
• CPC Class Codes: Y10S 148/159 Strain gauges

Abstract

A semiconductor pressure transducer includes a silicon substrate, a recessed portion in a major surface of the substrate, and a multiple level diaphragm overlying the recessed portion. A selectively etchable spacer material is employed when fabricating the diaphragm by forming successive layers of diaphragm material over the spacer material. Holes through the diaphragm are filled with the selectively etchable material thereby allowing the etching of the spacer material. Support posts can be provided in the recessed portion to help support the diaphragm.

Claims

1. A method of fabricating a semiconductor transducer having a multiple level diaphragm structure comprising the steps of

providing a semiconductor substrate,

forming a first layer of selectively etchable material on a surface of said substrate,

forming a second layer of a second material over said layer of selectively etchable material,

forming openings through said second layer and exposing said selectively etchable material,

forming additional selectively etchable material over limited positions of said first layer and in said openings as plugs having laterally extending portions,

forming a third layer of a third material over said second layer and and said additional selectively etchable material,

forming openings through said third layer and exposing said additional selectively etchable material, and

applying an etchant to remove said selectively etchable material thereby forming a multiple level diaphragm including said second and third layers of materials.

2. The method as defined by claim 1 wherein said openings through said second layer are offset from said openings through said third layer.

3. The method as defined by claim 2 and further including the step of forming an electrically insulative material on said surface of said substrate surrounding said layer of selectively etchable material prior to forming said first layer of second material, wherein the diaphragm structure is anchored to said insulative material.

4. The method as defined by claim 3 and further including the step of forming a plurality of support posts on said surface of said substrate, said support posts being positioned within said selectively etchable material.

5. The method as defined by claim 4 wherein said second and third layers are polycrystalline silicon and further including the step of sealing said diaphragm by oxidizing said polycrystalline silicon.

6. The method as defined by claim 1 and further including the step of forming an electrically insulative flange material on said surface of said substrate surrounding said layer of selectively etchable material prior to forming said first layer of second material, wherein the final diaphragm structure is anchored to said insulative material.

7. The method as defined by claim 6 and further including the step of forming a plurality of support posts on said surface of said substrate, said support posts being positioned within said selectively etchable material.

8. The method as defined by claim 7 wherein said substrate is silicon and said layers, said plugs, said flange material, and said posts are selected from the group consisting of (A) silicon, (B) polycrystalline silicon, (C) silicon dioxide, (D) silicon nitride, (E) metal silicide, (F) polymer, and (G) metal as follows:

first layer;

(A), (B), (C), (F), and (G)

second layer;

(B), (C), (D), (E), (F), and (G)

plugs;

(B), (C), (F), and (G)

third layer;

(B), (C), (D), (E), (F), and (G)

flange material;

(A), (B), (C), (D), (E), (F), and (G)

posts;

(A), (B), (C), (D), (E), (F), and (G).

9. The method as defined by claim 1 and further including the step of forming a plurality of support posts on said surface of said substrate, said support posts being positioned within said selectively etchable material.

10. The method as defined by claim 1 and further including the step of sealing said diaphragm.

11. The method as defined by claim 1 wherein said substrate is silicon and said selectively etchable material is undoped silicon, said layer of selectively etchable material overlying a doped layer of silicon in said substrate.

12. The method as defined by claim 11 wherein said layer of selectively etchable material is formed by vapor deposition.

13. The method as defined by claim 11 wherein said doped layer of silicon is formed by ion implantation.

14. The method as defined by claim 11 and further including the step of forming a plurality of support posts within the area of said selectively etchable material.

15. The method as defined by claim 11 and further including the step of sealing said diaphragm.

16. The method as defined by claim 1 wherein said substrate is silicon, said selectively etchable material is silicon dioxide, and said material in said second and third layers is polycrystalline silicon.

17. The method as defined by claim 16 in which the thickness of said laterally extensive portions of said plugs is less than the thickness of said first layer and in which the thickness of the polycrystalline silicon in said second and third layers is great enough to permit a thermally grown layer of silicon dioxide to form and fill the void left by etching of said laterally extensive portions of said plugs, said cavity formed by etching being sealed by oxidation of the polycrystalline silicon of said second and third layers.

18. The method as defined by claim 16 in which said cavity formed by etching is sealed by deposition of additional material in said holes formed in said third layer.

19. The method as defined by claim 1 in which some line-of-sight view may exist between said holes in said third layer and said holes in said second layer, but in which said view through said holes is small enough to permit sealing of said cavity by deposition of additional material in said holes in said third layer.

20. The method as defined by claim 1 in which some line-of-sight view may exist between said holes in said third layer and said holes in said second layer and in which there is no need to seal said cavity for a specific application.

21. The method as defined by claim 1 wherein said substrate is silicon, said material in said first layer is silicon, said plugs are polycrystalline silicon, said material in said second layer is silicon nitride, and said material in said third layer is selected from silicon nitride and silicon dioxide.

22. The method as defined by claim 1 and further including the step of removing substrate material beneath said diaphragm thereby exposing said diaphragm.