Multiprocessor multisystem communications network

• US 4,667,287 A
• Filed: 10/28/1982
• Issued: 05/19/1987
• Est. Priority Date: 10/28/1982
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Tandem Computers Incorporated (HP Inc.)
• Inventors: Peck, John C., Larson, Richard O., Allen, James C., Johnson, Hoke S. III, Fisher, Steven D., Bartlett, Wendy B.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/437,399
• Time in Patent Office: 1,664 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 709/234
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

A plurality of multiprocessor systems is arranged in a high speed network to allow any processor in one system to communicate with any processor in another system. The network is configured as a multi-node dual bidirectional ring having a multiprocessor system at each node. Packets of information may be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor in a selected direction between each successive transfer between neighboring nodes. The buffer locations are managed so that they can request an adjacent node to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.

Claims

1. A network of multiprocessor systems, including:

a plurality of multiprocessor systems, each of said systems containing at least one processor connected to an interprocessor bus,

a plurality of node interfaces, each connected to a respective one of said interprocessor busses, and connected to each other in the form of a ring by a data link,

a buffer memory in each of said node interfaces, having a plurality of storage locations for temporarily storing message packets to be transferred to any one of said processors in said network, said storage locations being partitioned into groups of storage locations, each one of said groups corresponding to a particular one of said processors in the network which is the destination processor for all of said message packets placed at locations therein,

control means in each of said node interfaces for controlling the transfer of said message packets into the buffer memory in its respective node interface from the data link connecting the respective interface node to its adjacent neighbor interface node and from the interprocessor bus connected to the respective interface node, and for controlling the transfer of said message packets out of the buffer memory in the respective node interface to the data link connecting the respective interface node to its adjacent neighbor interface node and to the interprocessor bus connected to the respective interface node

means, in each of said control means, for determining when a group of storage locations (in the buffer memory in its node interface) corresponding to a particular destination processor is full, and for halting the transfer of said message packets for that destination processor while said group of storage locations is full.