Method and apparatus for filtering high data rate signals
First Claim
1. Apparatus for filtering an analog signal, comprising:
- signal limiting means for hard limiting said analog signal to provide a constant amplitude signal having a first instantaneous value when the analog signal is above a predetermined level, and having a second instantaneous value when the analog signal is below said predetermined level, to thus remove amplitude fluctuations of said analog signal;
clock means for generating timing signals;
digital shift register means, actuated by said clock means and including a plurality of serially-arranged storage bits, for periodically sampling and storing said constant amplitude signal in a first bit as a logic 1 signal when the sampled constant amplitude signal has said first instantaneous value and as a logic 0 signal when the sampled constant amplitude signal has said second instantanteous value, the signal in each bit being shifted to a subsequent bit as a new signal is stored in the first bit and the signal stored in the last bit is lost, each bit having an output at which the signal stored in the bit can be sampled without changing the stored signal; and
signal processing means for sampling each combination of logic 1 and 0 signals stored in said shift register menas, and generating an output signal corresponding to calculated values of weighted sum for said shift register combinations.
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Abstract
Method and apparatus for filtering high data rate signals, using a digital type filter, without requiring an analog-to-digital converter or the multiplicaton of digital signals. The incoming signal is wideband filtered and then hard limited to produce a constant amplitude signal having either a first or second instantaneous value. The constant amplitude signal is periodically sampled and stored in a multi-bit digital shift register as logic 1 or 0 signals. In one embodiment, the logic 1 or 0 signals stored in the shift register bits are periodically read out, multiplied by respective weighting constants, and summed to provide a filtered analog output signal. In another embodiment, the combination of logic 1 and 0 signals stored in the shift register are periodically sampled and used to address a memory, which outputs a digital signal which is the calculated value of weighted sum for that shift register combination.
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Citations
14 Claims
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1. Apparatus for filtering an analog signal, comprising:
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signal limiting means for hard limiting said analog signal to provide a constant amplitude signal having a first instantaneous value when the analog signal is above a predetermined level, and having a second instantaneous value when the analog signal is below said predetermined level, to thus remove amplitude fluctuations of said analog signal; clock means for generating timing signals; digital shift register means, actuated by said clock means and including a plurality of serially-arranged storage bits, for periodically sampling and storing said constant amplitude signal in a first bit as a logic 1 signal when the sampled constant amplitude signal has said first instantaneous value and as a logic 0 signal when the sampled constant amplitude signal has said second instantanteous value, the signal in each bit being shifted to a subsequent bit as a new signal is stored in the first bit and the signal stored in the last bit is lost, each bit having an output at which the signal stored in the bit can be sampled without changing the stored signal; and signal processing means for sampling each combination of logic 1 and 0 signals stored in said shift register menas, and generating an output signal corresponding to calculated values of weighted sum for said shift register combinations. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An analog signal filtering method, comprising the steps of:
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hard limiting said analog signal to provide a constant amplitude signal having a first instantaneous value when the analog signal is above a predetermined level, and having a second instantaneous value when the analog signal is below said predetermined level, to thus remove amplitude fluctuations of said analog signal; periodically sampling said constant amplitude signal; storing each sampled constant amplitude signal in a first bit of a multi-bit digital shift register as a logic 1 signal when the sampled constant amplitude signal has said first instantaneous value and as a logic 0 signal when the sampled constant amplitude signal has said second instantaneous value, the signal in each bit being shifted to a subsequent bit as a new signal is stored in the first bit and the signal in the last bit is lost; periodically sampling, without altering or destroying, the combination of logic 1 and 0 signals stored in said shift register bits; and converting said sampled shift register combinations into an output signal corresponding to calculated values of weighted sum for said shift register combinations. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification