Space-division switching network for high data rate signals

• US 4,667,320 A
• Filed: 03/26/1985
• Issued: 05/19/1987
• Est. Priority Date: 04/02/1984
• Status: Expired due to Fees

• Current Assignee: Compagnie Industrielle des Telecommunications Cit-Alcatel SA
• Original Assignee: Compagnie Industrielle des Telecommunications Cit-Alcatel SA
• Inventors: Jaouen, Jean-Yves, Onno, Guy
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Scutch, III, Frank M.
• Application Number:
  US06/716,263
• Time in Patent Office: 784 Days
• Field of Search: 370/58, 370/63, 370/64, 340/825.79, 178/3
• US Class Current: 370/380
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence

Abstract

A multi-stage space-division switching network comprises groups of regenerators (RE1 to RE16) connected to input lines and to output lines of the switching network, it further includes groups of regenerators (RS1 to RS16) connected to a first end of intermediate links (LI1 to LI28) interconnecting two stages and groups of regenerators (R3.1 to R3.16) connected to the other ends of the intermediate links. A monitoring device comprises sampling devices (P) connected to the groups of regenerators and to a comparator circuit (CC). A main marker (MQP) receives connection instructions and sampling instructions and transmits these instructions to auxillary markers (MQ) which control the sampling circuits (P) and the switching circuits (C1, C2) of the switching network.

Claims

1. A space switching network for high data rate digital signals, the network having inlet lines and outlet lines connected thereto and comprising a plurality of stages with at least two consecutive stages being interconnected by a set of intermediate lines, each stage including switching matrices, said network further including regenerator modules, respectively at its inlets, at its outlets, and at each end of its intermediate lines, the regenerator modules at its inlets and at its outlets being connected to respective input lines and output lines, each regenerator module including means for recovering a clock rate from the high data rate digital signals passing therethrough and serving to correct amplitude, phase and wave shape degradation in the digital signals due to their passage through the inlet lines, the switching matrices and through the intermediate lines.

2. A switching network according to claim 1, further comprising a passive path monitoring device for bit-by-bit comparison of digital signals sampled at two points along a transmission channel, which two points delimit a portion of the said channel, said regenerator modules constituting sampling points for said digital signals, the monitoring device comprising sampling circuits connected to the regenerator modules and a comparator connected to the sampling circuits, the regenerator modules at the input to the switching network being connected to a first sampling circuit, the regenerator modules at the output of the switching network being connected to a second sampling circuit, each set of intermediate lines connecting two stages of the switching network being associated with an input sampling circuit and an output sampling circuit for the intermediate lines, said input sampling circuits being connected to the regenerator modules situated at the inputs of the intermediate lines and the said output sampling circuits being connected to to the regenerator modules situated at the outputs of said intermediate lines, each sampling circuit including sampling means for sampling the digital signal and a phase adjusting circuit for the sampled ditigal signal to provide independence from the propagation time of the digital signal between the two regenerator modules at the end of the portion being sampled, the comparator circuit comprising means for comparing the samples delivered by the sampling circuits associated with the regenerator modules of the said portion, means for recognizing that a transmission channel is properly established between the input and the output of the said portion, means for measuring the error rate over the said portion, and means for delivering a phase adjusting control signal, and means for recognizing when a channel is badly established over the said monitored portion.

3. A switching circuit according to claim 2, wherein the phase adjusting circuit is constituted by a NAND gate, first and second bistables, and a NOR gate, wherein the NAND gate has one input connected to the comparator circuit from which it receives a phase adjusting control signal and another input connected in the sampling circuit to a control circuit from which it receives a logic level 0 signal when the regenerator module to which it is connected is situated at the input end of a monitored portion and a logic level 1 signal when the regenerator module is situated at the output end of the monitored portion, wherein the first bistable has a clock input connected to the output of the NAND gate, a data input connected to receive a logic level 1 signal, and wherein the second bistable has a clock input connected to a clock recovery circuit in the sampling circuit which delivers a clock signal recovered from the digital signal being sampled, a data input connected to the output from the first bistable and has its output connected to the reset to zero of the first bistable and to one of the inputs of the NOR gate whose other input is connected to the clock recovery circuit and whose output is connected to the sampling means.

4. A switching network according to claim 2, wherein the sampling means are constituted by a divider and by a bistable, the divider having one input connected to the output from the phase adjusting circuit and the bistable having its clock input connected to the output from the divider, a data input receiving the digital signal for sampling and its output delivering samples from the digital signal to the comparator circuit.

5. A switching network according to claim 2, wherein the comparator circuit means for comparing the samples are constituted by a sample comparator having its inputs connected to each of the sampling circuits via a first line for conveying digital signal samples taken from the input to the monitored portion and via a second line for conveying digital signal samples taken from the output of the monitored portion, wherein the means for recognizing that a transmission channel is properly established between the input and the output of the portion being monitored are constituted by a coincidence counter and by a comparator, the counter being connected to a coincidence output from the sample comparator and the comparator being connected to the output from the coincidence counter and comparing the number of coincidences delivered by the coincidence counter with a fixed value to deliver a good connection signal when the number of coincidences reaches the said fixed value, wherein the means for measuring the error rate are consituted by an error counter having a count input connected to a non-coincidence output from the sample comparator and a control input connected to the output from the comparator of the means for recognizing that a channel is properly established, and wherein the means for recognizing that a transmission channel is badly established between the input and the output of the monitored portion are constituted by an AND gate, a non-coincidence counter, and a comparator, the AND gate having one input connected to the non-coincidence output from the sample comparator, an inverting input connected to the output from the comparator of the means for recognizing that a channel is properly established, and an output connected directly to the non-coincidence counter and via an inverter to a line which is connected to all the sampling circuits for conveying a phase adjusting control signal, the comparator being connected to the output from the non-coincidence counter and comparing the number of non-coincidences delivered by the non-coincidence counter with a fixed value and delivering a bad connection signal when the number of non-coincidences reaches the said fixed value.