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Method and apparatus for error detection and correction in systems comprising floppy and/or hard disk drives

  • US 4,667,326 A
  • Filed: 12/20/1984
  • Issued: 05/19/1987
  • Est. Priority Date: 12/20/1984
  • Status: Expired due to Term
First Claim
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1. In an error detection and correction apparatus comprising a series of stages, each of said stages having a first and a second network of exclusive OR gates, a single exclusive OR gate having a first input, a second input and an output, a memory device, means for selectively coupling said first input to said first network and said first location, means for coupling said output to said memory device, means for selectively coupling said second input to the output of the memory device in another stage and to said second network and means for coupling the output of said memory device in each stage to said second network;

  • a method for detecting and correcting errors in data being transferred between a first location and a second location comprising the steps of;

    (a) initializing the contents of the memory device in each of said stages;

    (b) transferring each byte in said series of bytes from said first location through said first network in each of said stages;

    (c) exclusively ORing the output of said first network in each of said stages with said output of said memory device in said other stage which was generated in response to a preceding byte in said series;

    (d) storing the results of said latter step in said memory device of said stage;

    (e) repeating steps (b)-(d) until each of said bytes in said series has been transferred through said series of stages and the contents of the memory device in each of said stages comprises a check sum;

    (f) storing said series of bytes and said check sum in the memory device in each of said stages to said second location;

    (g) initializing the contents of the memory device in each of said stages;

    (h) exclusively ORing each of said bytes in said series and said check sum stored therewith at said second location with an output from said second network of exclusive OR gates which is generated in response to the contents of the memory device in said stage;

    (i) storing the results of said latter step in said memory device;

    (j) repeating steps (h) and (i) until each of said bytes in said series and said check sum has been transferred from said second location through said series of stages and the contents of the memory device in each of said stages comprises a syndrome; and

    (k) providing an error detect signal if any one of said bytes in said syndrome comprises a predetermined logical level.

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