Time base equalizer and corrector (TIBEC) for video tape or disk machines in playback modes

• US 4,668,999 A
• Filed: 12/04/1984
• Issued: 05/26/1987
• Est. Priority Date: 12/04/1984
• Status: Expired due to Fees

• Current Assignee: Scitech Corporation
• Original Assignee: Scitech Corporation
• Inventors: De La Cierva, Juan Jr., De La Cierva, Juan Sr.
• Primary Examiner(s): McElheny, Jr., Donald
• Application Number:
  US06/677,975
• Time in Patent Office: 903 Days
• Field of Search: 360/14.1, 360/14.2, 360/14.3, 360/15, 360/36.1, 360/36.2, 360/70, 360/33.1, 358/335, 358/320, 358/337, 358/148, 358/149, 358/150, 358/151, 358/181, 358/182, 358/183, 358/185
• US Class Current: 386/307
• CPC Class Codes: G11B 2220/20 Disc-shaped record carriers
• CPC Class Codes: G11B 2220/90 Tape-like record carriers
• CPC Class Codes: G11B 27/002 Programmed access in sequence to a plurality of record carriers or indexed parts, e.g. tracks, thereof, e.g. for editing; transfer of record carriers from magazine G11B15/68, G11B17/10; G11B17/22
• CPC Class Codes: G11B 27/024 on tapes G11B27/028, G11B27/029 take precedence
• CPC Class Codes: G11B 27/028 with computer assistance
• CPC Class Codes: G11B 27/10 Indexing; Addressing; Timing or synchronising; Measuring tape travel
• CPC Class Codes: H04N 9/89 Time-base error compensation
• CPC Class Codes: Y10S 358/906 Hand-held camera with recorder in a single unit

Abstract

A time base video equalizer and/or corrector for video tape or disk machines including a precorrector and a postcorrector section. The device is driven by a master video source, corrected or not, and synchronization with a slave video machine is achieved for the operation of interfaced special effects video devices. The jitter and coherence imperfections of the master video signal are followed by the slave machine thereby equating or synchronizing their timing components.

Claims

1. A video signal processing device for equalizing the timing errors of a Slave Video tape recorder playback video signal to a Master Time Reference Video signal, and said slave recorder including external Sync and Subcarriers circuits, comprising:

A. first means for buffering and clamping said Master signal Time Reference Video having one output;

B. second means for separating the vertical, MV, horizontal, MH, and subcarrier MSC components of said Master Time Reference Video signal connected to said output of said first means for buffering and clamping said Master Time Reference Video signal;

C. driving means having three inputs connected to the three outputs of said components of said means for separating said vertical, horizontal and subcarrier components and receiving said components at said input and producing two outputs, a Master Delayed Vertical signal, MDV, and a Master Phased Subcarrier signal, MPSC, and said outputs being connected to said external Sync and Subcarrier circuits of said Slave Video tape recorder;

D. clock generator means having two inputs and one of said inputs being connected to said Master Subcarrier component output and the other input being connected to said Master Horizontal component output and so designed to produce three outputs wherein the first one, 2MSC, is similar to said MSC at twice its frequency, the second one is similar to MSC at an integer multiple of its frequency and the third one, MASC, is an alternating phase signal with the same frequency as MSC;

E. Master Coherence Generator means, having two inputs connected to said Master Horizontal, MH, and Master Alternating Subcarrier, MASC, signals, for generating a Master Horizontal Coherent, MHC, signal having the same repetition rate as said MH signal and further having its leading edge delayed so that it substantially coincides with the leading edge of the first MASC pulse after each MH pulse occurs;

F. Master Coherent start switch means for generating three coherent start signals, MCSR1, MCSR2 and MCSR3, having two inputs, using said MHC and MV signals as said inputs, wherein said start signals are triggered at the beginning of each video frame, MV pulses, by the leading edges of the first three MHC pulses so that said start signals are produced consecutively, and this cycle repeating itself until reset by the following MV pulse;

G. third means for buffering and clamping said Slave Video signal having one output;

H. fourth means for separating the vertical and horizontal components of said Slave Video signal connected to said output of said third means for buffering and clamping said Slave signal;

I. resync generator means for producing a slave resynchronized video, SRVID, signal having two inputs connected to the output, SVID, of said third means for buffering and clamping said Slave video signal and to the horizontal component, SH, output of said fourth means for separating said vertical and horizontal components of said Slave signal so that the leading edge of said Slave horizontal sync pulse component of said SRVID signal substantially coincides with the leading edge of SH and the pulse width of SRVID is constant and independent of the pulse width of said Slave Video signal;

J. three delay line sychronization means for generating three slave resynchronized delayed video output signals, SRDVID1, SRDVID2 and SRDVID3 and having each four inputs, three of said four inputs being connected to said 2MSC, MASC, SRVID and the remaining input in each of said delay line synchronization means being connected respectively to MCSR1, MCSR2 and MCSR3 signals and further including means for delaying said signals so that said resulting output signals SRVID1, SRVID2 and SRVID3 are delayed for a period of time such that the stored Slave Video restarts in near synchronization with the Master Time Reference Video signal; and

K. Slave Video reassembly switch means for commuting the output signals, SRDVID1, SRDVID2 and SRDVID3, of said delay line synchronization means and said reassembly switch means being controlled by any two of said MCSR1, MCSR2 and MCSR3 signals so that their logic state will determine which one of said output signals is to appear at the output of said switch reassembly means and connected to the output SPVID of said processing device.

2. The device set forth in claim 1 further including a postcorrector device, comprising:

L. fifth means for detecting the trailing edge of the horizontal sync pulse of the output SPVID of said processing device and producing a Precorrected Horizontal Trailing Edge signal, PCHT;

M. sixth means for delaying the Master Horizontal signal, MH, thereby producing a Master Delayed Horizontal signal, MDH, that has its leading edge delayed a time interval equal to the pulse width of the Slave Video Resynced H pulse of SRVID output signal of said resync generator means;

N. counter means having its input connected to said second output of said clock generator means and said counter means being adapted to be reset at the leading edge of the Master Horizontal signal, MH, and being also adapted to start counting when said MDH signal occurs and stops, holding its count, when said PCHT signal arrives thereby counting the amount of residual jitter in units of time equal to the period the selected multiple of the Master Subcarrier and holding the counter output until the next Master Horizontal leading edge arrives;

O. seventh means for separating the luminance component from said SPVID signal;

P. first switch means for selecting one of a plurality of inputs according to said counter output and further including first multi-tap delay means connected to said inputs so that the output of said means for separating the luminance component is routed through said first multi-top delay means and extracted from the tap selected by the counter output thereby adjusting the delay according to the amount of jitter detected by the counter means;

Q. eighth means for separating the chrominance component from said SPVID signal;

R. second switch means for selecting one of a plurality of inputs according to said counter output, and further including second multi-top delay means connected to said inputs so that the output of said eighth means for separating the chrominance component is routed through said second multi-top delay means and extracted from the tap selected by said counter output thereby adjusting the alignment of the chrominance information with the luminance information without losing the phase of the chrominance information;

S. ninth means for mixing the output of said first and second switch means;

T. Master blanking generator means receiving the Master Horizontal and Vertical signals, MH and MV, at its inputs generating at its output a composite Master blanking signal; and

U. tenth means for replacing the composite sync portion of the output signal of said ninth means with the composite sync portion of the Master Time Reference Video signal as controlled by said Master blanking signal.

3. A device as set forth in claim 1, further comprising means for measuring jitter in a Slave Video signal with respect to said Master Time Reference Video signal, comprising:

A. means for detecting the trailing edge of the reference point in the luma component of said Slave Video signal so that a Slave Horizontal Trailing edge signal, SHT, is produced;

B. means for delaying the horizontal sync component, MH, of said Master Time Reference Video signal thereby producing a master delay signal, MDH, that has its leading edge delayed a predetermined time interval;

C. means for generating a clock signal that is a predetermined multiple of the frequency of the subcarrier of said Master Time Reference Video signal; and

D. counter means having its input connected to said clock signal and being adapted to be reset at the leading edge of the horizontal sync component, MH, said Master Time Reference Video signal, and being also adapted to start counting when said MDH signal occurs and stops, holding its count, when said SHT signal arrives thereby counting the amount of jitter in units of time that are equal to the period of the multiple of the Master Subcarrier and holding the count on said counter means output until the next master horizontal leading edge arrives.

4. The device set forth in claim 3 further including:

E. means for separating the luminance component from said Slave Video signal;

F. means for separating the chrominance component from said Slave Video signal;

G. first selection switch means for selecting one of a plurality of inputs according to said counter output and further including first multi-tap delay means connected to said inputs so that the output of said means for separating the luminance component is routed through said first multi-top delay means and extracted from the tap selected by the counter output thereby adjusting the delay according to the amount of jitter detected by the counter so that the output of said first switch means is delayed to complement the jitter circuit;

H. second selection switch means for selecting one of a plurality of inputs according to said counter output, and further including second multi-top delay means connected to said inputs so that the output of said means for separating the chrominance component is routed second multi-top delay means and extracted from the tap selected by said counter output thereby adjusting the alignment of the chrominance information with the luminance information without losing the phase of the chrominance information;

I. means for mixing the outputs of said first and second selection switch means.