Non-linear echo cancellation of data signals

• US 4,669,116 A
• Filed: 12/09/1982
• Issued: 05/26/1987
• Est. Priority Date: 12/09/1982
• Status: Expired due to Fees

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Agazzi, Oscar E., Messerschmitt, David G.
• Primary Examiner(s): Rubinson, Gene Z.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/448,418
• Time in Patent Office: 1,629 Days
• Field of Search: 179/170.2, 179/170.6, 179/170.8, 370/32, 364/724
• US Class Current: 379/406.08
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04B 3/231 Echo cancellers using readout of a memory to provide the echo replica
• CPC Class Codes: H04B 3/238 using initial training sequence

Abstract

An echo cancellation circuit is disclosed for use with full-duplex data transmission systems. The echo canceller can operate in spite of time invariant non-linearities in the echo channel or in the implementation of the echo canceller itself (such as in D/A converters). The echo canceller receives an echo signal having linear and non-linear components and includes N linear tap weights for cancelling the non-linear components of that echo signal where M is greater than N but less than 2^N.

Claims

1. An echo cancellation circuit comprising

means connected to receive a first bit stream corresponding to a first transmitted multilevel data signal,

means connected to receive a second transmitted data signal, said second data signal including a echo portion of said first transmitted data signal having linear and non-linear components,

means for processing said first bit stream to generate an approximate echo replica of said echo portion of said second signal, said processing means including

means for forming a set of N linear tap output signals,

means for forming a set of M-N non-linear tap output signals wherein M is greater than N but less than or equal to 2N, and

logic means for summing said linear and non-linear output signals to yield said approximate echo replica.

2. An echo cancellation circuit as in claim 1 wherein said means for processing include

means for generating a digital representation of said echo portion in said second data signal,

means for converting said second data signal to a digital format to provide a digital format signal, and

digital circuit means for subtracting said digital representation from said digital format signal.

3. An echo cancellation circuit as in claim 1 wherein said means for processing include

means for generating a digital representation of said echo portion in said second data signal,

means for converting said digital representation to an analog representation of the echo replica to form an analog echo replica, and

analog circuit means for subtracting said analog echo replica from the second data signal.

4. An echo cancellation circuit as in claim 1 including

means for storing N past bits from said first bit stream,

means for combining said N bits with N tap weights thereby forming said set of N linear tap output signals,

means for combining said N bits with M-N non-linear tap weights thereby forming said set of M-N non-linear tap output signals, and

means for subtracting said approximate echo replica from said second data signal.

5. An echo cancellation circuit as in claim 4 including

means for receiving a set of two or more bits from the N bits in storage,

means for generating a logical combination output bit of said set of two or more bits,

means for generating a state signal which is either a first state or a second state in response to said output bit, and

means for multiplying said state signal by said M-N non-linear tap weights.

6. An echo cancellation circuit as a claim 5 wherein said logical combination is a module 2 summation and wherein said first and second states represent a +1 and a -1 respectively.

7. An echo cancellation circuit as in claim 5 wherein said logical combination is a logical AND and said first and second states represent a 1 and an 0 respectively.

8. In an echo cancellation circuit, an echo cancellation method comprising the steps of:

receiving a first bit stream corresponding to a first transmitted multilevel data signal,

receiving a second transmitted data signal, said second data signal including an echo portion of said first data signal having linear and non-linear components,

processing said first bit stream to generate an approximate replica of the echo signal portion of said second data signal, and

subtracting said approximate echo replica from the second data signal to yield a substantially echo-free replica of the second data signal, the method further including the steps of

forming a set of N linear tap output signals,

forming a set of M-N non-linear tap output signals wherein M is greater than N but less than or equal to 2^N, and

logically summing said linear and non-linear tap output signals to yield said approximate echo replica.