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Process for forming a self-aligned low resistance path in semiconductor devices

  • US 4,669,178 A
  • Filed: 05/23/1986
  • Issued: 06/02/1987
  • Est. Priority Date: 05/23/1986
  • Status: Expired due to Fees
First Claim
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1. A method of forming a guard ring in a silicon semiconductor device comprising the steps of:

  • (a) forming a first protective layer on the surface of a silicon wafer;

    (b) forming a second protective layer on the first protective layer;

    (c) defining an opening in the first protective layer and the second protective layer to expose a selected portion of the silicon wafer surface with the opening in the second protective layer being smaller than the opening in the first protective layer such that the second protective layer overhangs the first protective layer and protects a portion of the silicon wafer;

    (d) implanting a first impurity in a portion of the exposed silicon wafer surface the same size as the opening in the second protective layer and smaller than the opening in the first protective layer;

    (e) thermally growing a silicon dioxide layer on the entire exposed surface of the silicon wafer, wherein the thermally grown silicon dioxide layer is thicker over the area where the impurity has been implanted and thinner over the area where the impurity has not been implanted, thereby forming a central thicker silicon dioxide area and an annular thinner silicon dioxide area therearound;

    (f) implanting a second impurity, the second impurity being implanted through the thinner annular silicon oxide to create a guard ring in the silicon wafer around the perimeter of the thicker silicon dioxide layer which remains; and

    (g) removing any protective layer from the silicon wafer surface.

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