Method for producing a field effect transistor

• US 4,670,090 A
• Filed: 01/23/1986
• Issued: 06/02/1987
• Est. Priority Date: 01/23/1986
• Status: Expired due to Fees

• Current Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Original Assignee: Rockwell International Corporation
• Inventors: Lee, Chien-Ping, Chang, Mau-Chung F., Sheng, Neng-Haung
• Primary Examiner(s): Powell, William A.
• Application Number:
  US06/821,664
• Time in Patent Office: 495 Days
• Field of Search: 156/643, 156/644, 156/646, 156/652, 156/653, 156/656, 156/657, 156/659.1, 156/661.1, 156/662, 156/668, 29/571, 29/576 W, 29/578, 29/580, 29/591, 427/88-90, 430/313, 430/317, 430/318, 430/315, 430/314, 357/23.1, 357/23.6, 357/41, 357/49, 357/65
• US Class Current: 438/571
• CPC Class Codes: G03F 7/095 having more than one photosensitive layer G03F7/075 takes precedence
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66863 Lateral single gate transistors

Abstract

A method is disclosed which is capable of producing improved field effect transistors such as high electron mobility transistors and metal semiconductor field effect transistors. The method comprises a dual level photoresist deposition technique on a semiconductor wafer, in conjunction with a double lift-off and dummy gate procedure. In the process, T-bar shaped portions of overlying top and bottom photoresist layers are produced, one of such T-bar shaped portions forming a dummy gate. Metal is then deposited on the upper surface of the T-bar shaped portions and on the exposed surface of the substrate to form a source and a drain. In a first lift-off step the metal on the T-bar shaped portions and the underlying remaining top layer portions, are removed. An inorganic film such as SiO is then deposited on the remaining bottom layer portions and over the metal on the surface of the substrate. In a second lift-off step the SiO film on the remaining bottom layer portions and the underlying bottom layer portions are removed. The space between remaining portions of the SiO film on the substrate defines a gate opening of submicron size. The metal on the surface of the substrate beneath the inorganic film is then alloyed by treatment at high temperature, and gate metal is deposited over the gate opening. Metal can then be deposited on the SiO imprinted film to form interconnects to the source and drain.

Claims

1. A process for producing a field effect transistor comprising the steps of

depositing a bottom layer of a first photoresist on said wafer,

depositing a top layer of a second photoresist on said bottom layer,

exposing an image of said pattern on said top layer,

developing said top layer to remove exposed portions thereof,

exposing the bottom layer beneath the removed portions of said top layer under conditions undercutting the bottom layer beneath the edges of the remaining portions of said top layer,

developing the bottom layer to remove the exposed portions thereof, and forming T-bar shaped remaining unexposed portions of overlying top and bottom layers,

depositing metal on the upper surface of said T-bar shaped portions and on the exposed surface of said wafer to form a drain and a source,

lifting off the metal on said T-bar shaped portions together with the underlying remaining top layer portions,

depositing an inorganic film on the remaining portions of the bottom layer and over the metal on the surface of the wafer,

lifting off the inorganic film on the remaining bottom layer portions together with said bottom layer portions, and

depositing the gate in the space between remaining portions of the inorganic film on said wafer defining the gate.

2. The process of claim 1, wherein said bottom layer is a polymethylmethacrylate layer and said top layer is a positive photoresist.

3. The process of claim 2, wherein said bottom layer is exposed to deep UV flood exposure, scattering of light beneath the edges of said remaining portions of said top layer to provide said undercutting beneath the edges of said remaining top layer portions.

4. The process of claim 1, wherein a space is left between the outer edges of the metal deposited on the surface of the wafer and the adjacent bottom layer portions of the T-bar shaped portions, defined by the undercut formed beneath the top layer portions of said T-bar shaped portions.

5. The process of claim 4, wherein said inorganic film deposited on the metal on the surface of the wafer envelopes around and covers the outer edges of the metal in the space left between the outer edges of the metal and the adjacent bottom layer portions of the T-bar shaped portions.

6. The process of claim 1, wherein the first lift-off step is carried out in a solvent capable of removing the remaining top layer portions containing the metal, and the second lift-off step is carried out in a solvent capable of removing the remaining bottom layer portions containing the inorganic film.

7. The process of claim 1, said metal comprising a first layer of gold, germanium eutectic alloy and a second layer of nickel over said first layer.

8. The process of claim 1, said inorganic film being a SiO_x film, where x is 1 or 2.

9. The process of claim 1, including subjecting the metal on the surface of the wafer to elevated temperature sufficient to cause alloying of said metal.

10. A self-aligned process for production of high electron mobility transistors having good transconductance and good subthreshold characteristics, which comprises the steps of:

depositing a bottom layer of a first polymethylmethacrylate photoresist on a high electron mobility GaAs/GaAlAs substrate,

depositing a second top layer of positive photoresist on said bottom layer,

exposing the top layer under a pattern,

developing said top layer to remove exposed portions thereof,

exposing the bottom layer beneath the previously exposed portions of the top layer, with deep UV flood exposure, scattering of light beneath the edges of said remaining portions of said top layer to undercut the edges of the remaining portions of said top layer,

developing the bottom layer to remove the exposed portions thereof, and forming T-bar shaped remaining unexposed portions of overlying top and bottom layers, one of said T-bar shaped portions forming a T-bar dummy gate,

depositing a first metal on the upper surface of said T-bar shaped portions and on the exposed surface of said substrate to form a source and a drain, and leaving a space between the outer edges of the metal deposited on the surface of the substrate and the adjacent bottom layer portions of the T-bar shaped portions, defined by the undercut formed beneath the top layer portions of said T-bar shaped portions,

lifting off the metal on said T-bar shaped portions including said T-bar dummy gate, together with the underlying top remaining layer portions by treatment in a solvent for said positive photoresist,

depositing a SiO film on the remaining portions of the bottom layer and over the on the surface of the substrate, said film covering the outer edges of the metal in the space left between the outer edges of the metal and the adjacent bottom layer portions of the T-bar shaped portions,

lifting off the SiO film on the remaining bottom layer portions together with said bottom layer portions, by treatment in a solvent for said polymethylmethacrylate bottom layer portions, and

depositing gate metal on the exposed surface of said substrate in the space between remaining portions of the SiO film to define the gate.

11. The process of claim 10, said first metal comprising a first layer of gold, germanium eutectic alloy and a second layer of nickel over said first layer.

12. The process of claim 11, including subjecting the first metal on the surface of the substrate to elevated temperature sufficient to cause alloying of said metal and form ohmic contacts.

13. The process of claim 12, including depositing metal on the silica imprinted portions on the substrate to form interconnections to said source and drain.