Substrate bias generator with power supply control means to sequence application of bias and power to prevent CMOS SCR latch-up

• US 4,670,668 A
• Filed: 05/09/1985
• Issued: 06/02/1987
• Est. Priority Date: 05/09/1985
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Liu, Wei-Ti
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): HUDSPETH, DAVID R
• Application Number:
  US06/732,529
• Time in Patent Office: 754 Days
• Field of Search: 307/200 B, 307/355, 307/579, 307/585, 307/591, 307/592, 307/594, 307/296 R, 307/297
• US Class Current: 327/537
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

A bias generator circuit includes a first high voltage for biasing a N-well region and a second delayed and lower voltage biasing a source region of a P-channel field-effect transistor so as to increase latch-up immunity. The generator circuit includes a high voltage generator and a multiplier circuit responsive to a power supply voltage for generating a first voltage level for biasing the N-well region. A delay network is responsive to the first voltage for generating a delay voltage. A level detection circuit is responsive to the delay voltage and the power supply voltage for generating a control signal when the delayed voltage reaches a predetermined level. A control device is responsive to the control signal for generating a second voltage for biasing the source region of the P-channel field-effect transistor. The second voltage level is delayed and lower than the first voltage level so that the PN junction is reverse biased to increase latch-up immunity.

Claims

1. A bias generator circuit which produces a first higher voltage for biasing a N-well region and a second delayed and lower voltage for biasing a source region of a P-channel field-effect transistor formed within the N-well region so as to increase latch-up immunity, said generator circuit comprising:

means for generating a power supply voltage;

high voltage means responsive to said power supply voltage for generating a first voltage level for biasing the N-well region;

delay means responsive to said first voltage level for generating a delayed voltage;

level detector means responsive to said delayed voltage and said power supply voltage for generating a control signal when said delay voltage reaches a predetermined level; and

control means responsive to said control signal for generating a second voltage level for biasing the source region of the P-channel field-effect transistor, said second voltage level being delayed and lower than said first voltage level so that the source region and the N-well region defining a PN junction is reverse biased to increase latch-up immunity.

2. A bias generator circuit as claimed in claim 1, wherein said high voltage means comprises a high voltage generator and a multiplier circuit which pumps the power supply voltage to the first voltage level, said multiplier circuit being coupled to an output voltage of said high voltage generator.

3. A bias generator circuit as claimed in claim 2, wherein said multiplier circuit includes means for maintaining the first voltage level to be equal to the power supply voltage when said output voltage of said high voltage generator is lower than said power supply voltage and means for increasing the first voltage level to be equal to said output voltage of said high voltage generator when said output voltage is higher than said power supply voltage.

4. A bias generator circuit as claimed in claim 1, wherein said delay means comprises a pair of first and second inverters and a RC network.

5. A bias generator circuit as claimed in claim 4, wherein each of said inverters is formed of a P-channel MOS transistor and a N-channel MOS transistor.

6. A bias generator circuit as claimed in claim 4, wherein said RC network is formed of a pair of N-channel MOS transistors and a pair of capacitors.

7. A bias generator circuit as claimed in claim 1, wherein said level detector means comprises a pair of P-channel MOS transistors and a series connection of three N-channel MOS transistors.

8. A bias generator circuit as claimed in claim 1, wherein said control means includes a P-channel MOS transistor whose gate electrode is responsive to said control signal for generating said second voltage level to said source region only after said first higher voltage level has been already applied to the N-well region.

9. A bias generator circuit as claimed in claim 2, wherein said multiplier circuit comprises a pair of first and second N-channel MOS output transistors having their sources connected together and to a first output terminal for supplying the first voltage level, the drain of said first transistor being connected to the output voltage of the high voltage generator, the drain of the second transistor being connected to the power supply voltage, the gate of the first transistor being coupled to receive a first pumped voltage, the gate of the second transistor being coupled to receive a second pumped voltage.

10. A bias generator circuit as claimed in claim 9, further comprising a first charge transfer transistor for generating the first pumped voltage and second charge transfer transistor for generating the second pumped voltage.

17. A bias generator circuit as claimed in claim 1, wherein said generator circuit is formed on a single silicon chip of a semiconductor integrated circuit.

11. A field-effect integrated circuit which is responsive to a first higher voltage for biasing a well-region and a second delayed and lower voltage for biasing a source region of a field-effect transistor comprising:

a semiconductor substrate of a first conductivity type having at least one well-region of a second conductivity type embedded in said substrate, two regions of said first conductivity type being embedded within said at least one well-region for forming the source and drain regions of the transistor of said first conductivity type, one region of said second conductivity type also being embedded within said at least one well-region of said second conductivity type;

means formed of a high voltage generator and a multiplier circuit for generating and applying a first bias voltage to said at least one well-region of said second conductivity type; and

means responsive to said first bias voltage for generating and applying a second bias voltage to said source of said transistor of said first conductivity type, said second bias voltage being delayed and lower in level than said first bias voltage so as to increase latch-up immunity.

12. A field-effect integrated circuit as claimed in claim 11, wherein said first conductivity type is P-conductivity type and said second conductivity type is a N-conductivity type.

13. A field-effect integrated circuit as claimed in claim 11, wherein said means for generating and applying said second bias voltage includes a delay network, a level detector circuit, and a control device.

14. An integrated circuit comprising:

a substrate of a first conductivity type;

a well-region of a second conductivity type being embedded within said substrate;

two regions of said first conductivity type being embedded within said well-region for forming the source region and drain region of a transistor of said first conductivity type;

a region of said second conductivity type being also embedded within said well-region, said well-region being in physical contact with said source region for forming a PN junction;

means for applying a first voltage level to said well-region and for applying a second level to said source region, said second voltage being delayed and having a lower voltage level relative to said first voltage level to maintain said PN junction in a reverse biased condition so as to increase latch-up immunity;

said means for applying said first and second voltage levels including a high voltage generator, a multiplier circuit, a delay network and a level detection circuit; and

control means having a conduction path coupled between a power supply voltage and said source region and a control electrode responsive to said first voltage level for controlling the conductivity across said conduction path, said control means applying said second voltage level to said source region only after the first higher voltage level has already been applied to the well-region.

15. An integrated circuit as claimed in claim 14, wherein said first conductivity type is a P-conductivity type and said second conductivity type is a N-conductivity type.

16. An integrated circuit as claimed in claim 14, wherein said control means includes a P-channel MOS transistor.