High-speed transient pulse height counter

• US 4,670,711 A
• Filed: 02/04/1985
• Issued: 06/02/1987
• Est. Priority Date: 02/04/1985
• Status: Expired due to Fees

• Current Assignee: The Boeing Co.
• Original Assignee: The Boeing Co.
• Inventors: Daniels, James W.
• Primary Examiner(s): Tokar, Michael J.
• Application Number:
  US06/697,954
• Time in Patent Office: 848 Days
• Field of Search: 324/77 R, 324/77 A, 324/77 D, 324/77 E, 324/73 R, 324/73 AT, 324/77 G, 324/140 R, 324/103, 324/113, 307/229, 328/116, 340/172.5, 340/857, 364/518
• US Class Current: 324/76.16
• CPC Class Codes: G01R 29/033 giving an indication of the number of times this occurs , i.e. multi-channel analysers (the characteristic being frequency)

Abstract

A pulse height counter for counting the number of excursions of an incoming analog signal through each of a plurality of amplitude ranges. The pulse height counter automatically records not only the number of excursions through each amplitude level, but also records the number of amplitude excursions for each of a plurality of intervals. An analog input signal to be analyzed is synchronously applied to each of a plurality of comparators (VCO - VCF), which have reference voltages that are related so as to define predetermined amplitude ranges. During a count cycle, a counting circuit (CO - CF) receives the output signals from each of the comparators and produces a set of count data that indicates the number of occurrences of the analog input signal within each of the amplitude ranges. The count cycle is followed by a write cycle, during which the count values are stored in separate data bins, or event memories (MO - MF). The addresses of the memories are related to separate intervals during which count data for individual input signals can be stored. The addresses are shared by the memories so that, for a given interval, the count data for each of the amplitude ranges are stored at the same address but in a separate one of the memories. Thus, the count data for each of the amplitude ranges recorded during a predetermined interval may be recalled and displayed (18, 20, 22) during a readout mode of operation. The timing of the counting and writing cycles of operation is controlled by a count timer (32), a write timer (34), and an address counter (38) included in a timing and control circuit (10). Upon receipt of the analog input signal, the count timer is triggered to enable transfer of the outputs of the comparators to the counters. At the conclusion of the count cycle, the comparator outputs are disabled and the memories are enabled so that the count data may be transferred thereto. At the conclusion of the write cycle, the memories are disabled from receiving further count data and the counters are automatically reset so that new count data can be created upon receipt of a subsequent input signal. Substantially simultaneously with the resetting of the counters, the commonly shared address is incremented by 1 so that the count data for the next-received input signal is stored in the respective memories at the next successive storage location.

Claims

1. A pulse height counter, comprising:

a comparison circuit having a plurality of comparators connected to synchronously receive an analog input signal, each of said comparators comparing the amplitude of said analog input signal with a predetermined reference voltage and, in accordance therewith, producing a comparator output signal, the reference voltages of said comparators being related so as to define predetermined amplitude ranges for said analog input signal;

a counting circuit connected to said comparison circuit to synchronously receive the comparator output signal of each of said comparators and, in accordance therewith, produce a set of count data that indicates the number of occurrences of said analog input signal within each of said predetermined amplitude ranges;

a storage circuit having a plurality of data bins, there being a plurality of data bins for each of said predetermined amplitude ranges, said data bins being arranged in groups that are defined by sequential addresses, each of said addresses corresponding to a predetermined time duration, said storage circuit being connected to receive said set of count data and store the count data for each of said predetermined amplitude ranges in a separate one of said bins; and

timing and control means for receiving said analog input signal and, in response to receipt thereof, in sequence;

(a) enabling said counting circuit to receive the comparator output signals of said comparators and produce said set of count data;

(b) disabling said counting circuit from receiving said count data;

(c) causing said storage circuit to store said count data in the group of data bins corresponding to the first one of said addresses; and

(d) changing said address to the next sequential address and repeating operations (a), (b), and (c) in sequence to cause said storage circuit to store count data for the next time duration in the next group of data bins.

2. The pulse height counter of claim 1, wherein said counting circuit includes a plurality of resettable counters, one of said counters being associated with each of said plurality of comparators, each of said resettable counters being connected to receive the comparator output signal from its associated comparator and, in accordance therewith, produce the count data for one of said predetermined amplitude ranges.

3. A pulse height counter comprising:

a comparison circuit having a plurality of comparators connected to synchronously receive an analog input signal, each of said comparators comparing the amplitude of said analog input signal with a predetermined reference voltage and, in accordance therewith, producing a comparator output signal, the reference voltages of said comparators being related so as to define predetermined amplitude ranges for said analog input signal;

a counting circuit connected to said comparison circuit to synchronously receive the comparator output signal of each of said comparators and, in accordance therewith, produce a set of count data that indicates the number of occurrences of said analog input signal within each of said predetermined amplitude ranges; and

a storage circuit having a plurality of memories, said storage circuit being connected to receive said set of count data and store the count data for eachh of said predetermined amplitude ranges in a separate one of said memories, one of said memories being associated with each of said plurality of counters, each of said memories having a plurality of storage locations, each of said storage locations being defined by an address, said addresses being shared by said memories so that the count data for each of said predetermined amplitude ranges is stored at the same address but in a separate one of said memories.

4. The pulse height counter of claim 3, wherein said timing and control means includes:

a count timer, said count timer being triggered by the receipt of said analog input signal to produce a count signal that is applied to said comparison circuit to cause the transfer of said comparator output signals to said counters during a count time interval; and

a write timer connected to receive said count signal and, in accordance therewith, produce a write signal, said write signal being applied to said plurality of memories to enable said plurality of memories to store said count data at said addresses during a write time interval, said write time interval being subsequent to said count time interval, said write signal being applied to said counters to reset said counters upon conclusion of said write time interval.

5. The pulse height counter of claim 4, wherein said timing and control circuit includes an address counter, said address counter being connected to receive said write signal and, in accordance therewith, produce a common address signal related to the addresses of the plurality of storage locations included in said memories, said common address signal being applied to each of said memories.

6. A pulse height counter, comprising:

a comparison circuit having a plurality of comparators connected to synchronously receive a train of individual transient pulses, each of said comparators comparing the amplitude of said transient pulses with a predetermined reference voltage and, in accordance therewith, producing a comparator output signal, the reference voltages of said comparators being related so as to define predetermined amplitude ranges for said transient pulses;

a counting circuit connected to said comparison circuit to synchronously receive the comparator output signal of each of said comparators and, in accordance therewith, produce a set of count data that indicates the number of occurrences of said transient pulses within each of said predetermined amplitude ranges, said counting circuit including a plurality of resettable counters, one of said counters being associated with each of said plurality of comparators, each of said resettable counters being connected to receive the comparator output signal from its associated comparator and, in accordance therewith, produce the count data for one of said predetermined amplitude ranges;

a storage circuit having a plurality of memories, said storage circuit being connected to receive said set of count data and store the count data for each of said predetermined amplitude ranges in a separate one of said memories, one of said memories being associated with each of said plurality of counters, each of said memories having a plurality of storage locations, each of said storage locations being defined by an address, said addresses being shared by said memories so that the count data of said predetermined amplitude ranges is stored at the same address but in a separate one of said memories; and

timing and control means for receiving said transient pulses and, in response to receipt thereof, in sequence;

(a) enabling said counting circuit to receive the comparator output signals of said comparators and produce said set of count data;

(b) disabling said counting circuit from receiving said count data; and

(c) causing said storage circuit to store said count data in said memories, said timing and control means including;

a count timer, said count timer being triggered by the receipt of each of said transient pulses to produce a count signal that is applied to said comparison circuit to cause the transfer of said comparator output signals to said counters during a count time interval;

a write timer connected to receive each of said count signals and, in accordance therewith, produce a write signal, said write signal being applied to said plurality of memories to enable said plurality of memories to store said count data at said addresses during a write time interval, said write time interval being subsequent to said count time interval, said write signal being applied to said counters to reset said counters upon conclusion of said write time interval; and

an address counter, said address counter being connected to receive said write signals and, in accordance therewith, produce a plurality of common address signals related to the addresses of the plurality of storage locations included in said memories, said common address signals being applied to each of said memories, said common address signals being changed in sequence upon receipt of said write signals to advance each of the memories in said storage circuit to its next storage location so that the count data for each of said transient pulses is stored in stepped sequence in particular storage locations in said memories, said storage locations being related to said common address signals.

7. The pulse height counter of claim 6, further including readout means connected to said address counter and to said memories for sequentially reading out the count data stored in each of the storage locations of said memories.