High storage capacity associative memory

• US 4,670,858 A
• Filed: 06/07/1983
• Issued: 06/02/1987
• Est. Priority Date: 06/07/1983
• Status: Expired due to Fees

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Almy, Thomas A.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/502,047
• Time in Patent Office: 1,456 Days
• Field of Search: 365/49, 364/200
• US Class Current: 365/49.17
• CPC Class Codes: G06F 16/90339 by using parallel associative memories or content-addressable memories
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

An associative memory having a large storage capacity which also has the capability of being used as a conventional memory, i.e. accessed by physical location. A memory array (11) is accessed in conventional fashion by an address decoder (15). A mask/data drive circuit (13) controls the loading/reading of the memory array (11) when the device is in a conventional mode, and operates on the same pins to provide mask and search data when the drive is in the associative mode. In the associative mode, a plurality of match detect (17) circuits, one for each word location in memory (11), receive the output signals from the memory array (11). The match detect circuits (17) prioritize the output match signals from memory (11) and provide an output indicating the first or lowest word in memory (11) having a match. An address encoder (19) is responsive to the prioritized match output (if any) from the match detect circuits (17) to determine the physical location in memory (11) containing the matched word.

Claims

1. An associative memory device capable of both conventional operation and associative operation, comprising:

a memory array, including first means for searching the data in the memory associatively to match words in accordance with a given search pattern;

second means coupled to the memory array for accessing said memory array by physical location;

third means coupled to the memory array for loading data into said memory array and reading data from said memory array when the memory device is enabled for conventional operation, and for providing a search pattern and a masking signal to said memory array and for accessing matched words in said memory array when the memory device is enabled for associative operation;

a plurality of match detect circuit means coupled to the memory array, one for each word location in said memory array, said plurality of match detect means for providing an output signal associated with the location of the first match in said memory array means; and

fourth means coupled to said match detect circuit means for determining the physical location in said memory array containing said first match.

2. An apparatus of claim 1, wherein the loading/reading of data in the conventional operation of said memory array is accomplished through the same pin connections used for the search pattern and the masking signal in the associative operation of said memory array.

3. An apparatus of claim 1, further including fifth means coupled to the second means for enabling the second means only when said memory array is to operate conventionally and sixth means coupled to the fourth means for enabling said fourth means only when said memory array is to operate associatively.

4. An apparatus of claim 1, wherein said match detect circuit means includes seventh means for detecting multiple matches within said memory array and providing an output indication thereof.

5. An apparatus of claim 4, wherein each match detect circuit means includes eighth means for applying indications of a match and multiple match to the next successive match detect circuit means.

6. An apparatus of claim 1, wherein said match detect circuit means includes ninth means for providing only the first match indication to said fourth means and tenth means for insuring that the output signals of the remaining match detect circuit means applied to said fourth means do not indicate a match.

7. An apparatus of claim 6, further including tenth means for providing an indication of a match from one selected match detect circuit means to a match detect circuit means beyond the next successive one.

8. An apparatus of claim 1, including eleventh means for cascading each memory element in said memory array, to increase the size of the memory device.

9. An apparatus of claim 8, further including a plurality of CAM memory means and a plurality of RAM memory means, each RAM memory means being uniquely associated with a CAM memory means, said CAM memory means capable of operating conventionally and associatively, said RAM memory means operating conventionally at all times, each CAM memory means including twelfth means for selecting its associated RAM memory means when said each CAM memory means is enabled.

10. An associative memory, comprising:

an associative memory array, including first means for searching the data in the memory associatively for matching words in accordance with a given search pattern;

second means coupled to the memory array for providing a search pattern and a masking signal to said memory array and for accessing matched words in said memory array;

a plurality of match detect circuit means, one for each word location in said memory array, said plurality of match detect circuit means for providing an output signal associated with the location of the first match in said memory array means; and

third means coupled to said match detect circuit means for determining the physical location in said memory array containing said first match.

11. An apparatus of claim 10, wherein said plurality of match detect circuit means includes fourth means for detecting multiple matches within said memory array and providing an indication thereof.

12. An apparatus of claim 11, wherein each match detect circuit means includes fifth means for applying indications of a match and multiple match to the next successive match detect circuit means.

13. An apparatus of claim 10, wherein said match detect circuit means includes sixth means for providing only the first match indication to said third means and seventh means for insuring that the output signals of any other match detect circuit means applied to said third means do not indicate a match.

14. An apparatus of claim 13, further including eighth means for providing an indication of a match from one selected match detect circuit means to a match detect circuit means beyond the next successive one.