Reliable synchronous inter-node communication in a self-routing network
First Claim
1. A packet switching network for communicating packets from network input ports to network output ports and each of said packets comprising routing information, said network comprising:
- a plurality of stages each comprising a plurality of switch nodes;
said plurality of stages interconnected by a plurality of interstage links;
each of said switch nodes comprising a plurality of input means and output means;
each of said switch nodes further comprises a plurality of intra-node links;
each input means of each of said switch nodes interconnected by a set of said intra-node links to all of the output means of the same switch node;
each output means of each switch node of an upstream stage interconnected via one of said plurality of interstage links to an individual input means of a switch node of a downstream stage;
one of said input means of a switch node of a downstream stage comprising means for generating packet clock signals for transmission to the output means of a switch node of the upstream stage via the interstage link upon said one of said input means having present capacity to receive a packet;
one of said output means of said switch node of said upstream stage responsive to receipt of said packet clock signals for transferring one of said packets to said one of said input means of said switch node of said downstream stage; and
said one of said output means of said switch node of said upstream stage comprises means responsive to the receipt of said packet clock signals from said one of said input means of said switch node of said downstream stage within a predefined amount of time following the end of transmission of said one of said packets for transmitting error information.
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Abstract
A communication method and packet switching network in which self-routing packets are communicated among stages of switching nodes via inter-stage links whereon data of the packets is transmitted in one direction and the packet clocking signals are transmitted in the other direction. Upon having the capability to accept a packet from one of the inter-stage links, a switch node transmits the packet clock signals to the upstream stage connect to that link indicating the present capacity to accept a packet. Furthermore, each switch node after receiving the end of a packet from an upstream stage times for a predefined amount of time before commencing the transmission of the packet clocking signals. That delay allows the transmitting switch node in the upstream stage to determine that the link and the downstream node are functioning correctly since continued transmission of the packet clock signals indicates that the packet had not been received or that downstream node had incorrectly responded to receipt of the packet. If a malfunction is detected, an error indication is transmitted to the computer controlling the switching network. Furthermore, upon receipt of a system reset signal, all switch nodes immediately transmit the packet clock signals to upstream stages; and the switch nodes in the upstream stages transmit the error indication if the packet clock signals are not received over a particular link within the predefined amount of time.
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Citations
21 Claims
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1. A packet switching network for communicating packets from network input ports to network output ports and each of said packets comprising routing information, said network comprising:
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a plurality of stages each comprising a plurality of switch nodes; said plurality of stages interconnected by a plurality of interstage links; each of said switch nodes comprising a plurality of input means and output means; each of said switch nodes further comprises a plurality of intra-node links; each input means of each of said switch nodes interconnected by a set of said intra-node links to all of the output means of the same switch node; each output means of each switch node of an upstream stage interconnected via one of said plurality of interstage links to an individual input means of a switch node of a downstream stage; one of said input means of a switch node of a downstream stage comprising means for generating packet clock signals for transmission to the output means of a switch node of the upstream stage via the interstage link upon said one of said input means having present capacity to receive a packet; one of said output means of said switch node of said upstream stage responsive to receipt of said packet clock signals for transferring one of said packets to said one of said input means of said switch node of said downstream stage; and said one of said output means of said switch node of said upstream stage comprises means responsive to the receipt of said packet clock signals from said one of said input means of said switch node of said downstream stage within a predefined amount of time following the end of transmission of said one of said packets for transmitting error information. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A switch node for utilization in a packet switching network having a plurality of stages with each of said stages interconnected to an upstream stage by a first plurality of interstage links and to a downstream stage by a second plurality of interstage links and each stage comprising a plurality of said switch nodes for the communication of packets and, each of said plurality of said switch nodes interconnected to said upstream stage by a set of said first plurality of interstage links and to said downstream stage by a set of said second plurality of interstage links, and said switch node comprising:
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a plurality of input means for receiving packets from an upstream stage of said network via the set of said first plurality of interstage links; a plurality of output means for communicating packets from said switch node to a downstream stage via the set of said second plurality of interstage links; a plurality of intra-node links; each input means interconnected by a set of said intra-node links to all of said output means; one of said input means comprises means responsive to the present capacity of said one of said input means to receive a packet for generating a present capacity signal; means responsive to the generation of said present capacity signal for transmitting packet clocking signals from said one of said input means to said upstream stage on one link of said set of said first plurality of interstage links; means responsive to one of said packets from said upstream stage for storing said one of said packets; means further responsive to the storing of said one of said packets for requesting via one of said intranode links the transfer of said one of said packets by said one of said output means to said downstream stage via one link of said set of said second plurality of interstage links; and said one of said output means controlled by the transfer request and receipt of the packet clock signals from said downstream stage via said one link of said set of said second plurality of interstage links to communicate said one of said packets to said downstream stage via said one link of said set of said second plurality of interstage links. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. Error checking and control facilities for switch nodes of a packet switching network for the communication of packets and each of said nodes comprising a plurality of input means for receiving packets from an upstream one of said switch nodes and a plurality of output means for communicating packets from the switch node to a downstream switch node, said facilities comprising:
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means in a downstream switch node responsive to one of said input means having the present capacity for receiving a packet for transmitting packet clocking signals from said one of said input means to an upstream node; one of said output means in said upstream switch node comprising means for internally storing one of said packets; first means for counting by module 3 in response to system clock signals; a set of flip-flops to temporarily retain packet data of said one of said packets; means responsive to said system clock signals for storing said one of said packets from said internal storing means into said set of flip-flops under the direction of the contents of said module 3 counting means; second means for counting by module 3 in response to said packet clock signals from said one of said input means; means responsive to said second module 3 counting means for sequentially reading the packet data from said set of said flip-flops for transfer to said one of said input means of said downstream switch node; said one of said downstream switch nodes further comprises another internal storing means for storing the transferred packet data; means responsive to the end of transmission of said packet data for ceasing to transmit said packet clock signals to said upstream switch node; said upstream switch node further comprises means responsive to the end of transmission of said packet data for timing for a predefined period of time; and means responsive to said timing for generating an error signal upon said packet clocking signals being received during the entire length of said predefined time period.
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19. A method of switching packets by a switching network having switching stages each comprising a plurality of switch nodes and each of said packets comprising address routing information and each of said switch nodes comprising a plurality of input means and output means and a plurality of links each interconnecting an individual output means of a switch node of an upstream stage to an individual input means of a switch node of a downstream stage, comprising the steps of:
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generating packet clock signals by one of said input means of the downstream stage for transmission to the output means of the upstream switch node via the interconnecting link upon said one of said input means having present capacity to receive one of said packets; transferring said one of said packets in response to said packet clock signals by said upstream switch node to said downstream switch node; timing for a predefined amount of time after the end of transmission of said one of said packet by said upstream switch node; and transmitting error information by said upstream switch node in response to receipt of said packet clock signals from said downstream switch node within said predefined amount of time. - View Dependent Claims (20, 21)
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Specification