Matrix control circuit for a memory display
First Claim
1. Matrix control circuit for a memory-type visual display with k column inputs and r row inputs for k times r display elements comprising:
- an m-bit serial digital video input receiving a signal defining sequentially one out of 2m brightness levels for each display element of a row y (y=1, 2, . . . , r) of display elements during successive video line times Ty-1 within a frametime that is at least equal to r times a video line time;
a series-parallel converter connected to the digital video input, having k times m column outputs corresponding to m bits for each column;
a video memory for storing column brightness information, having k times m information inputs which are coupled to the corresponding outputs of the series-parallel converter and k information outputs connected to the k corresponding column inputs of the display;
a Y-selection circuit having r selection outputs connected to the corresponding r row inputs of the display, the Y-selection circuit providing (M+1) selection pulses to each row of the display for setting or resetting the memory-type display elements of that row;
a timing circuit having at least one clock signal output for supplying a clock signal to clock signal inputs of the video memory and of the Y-selection circuit and a reset signal output for supplying a reset signal to reset signal inputs of the video memory and of the Y-selection circuit;
said video memory comprising a number of k column memories, each having a number of m column shift registers of respectively bj bits (j=1, 2, . . . , m), each column shift register having an input that is coupled to the corresponding information input for the corresponding column, a column shift register output and a line time shift signal input for a line time shift signal shifting all column shift registers substantially at the end of each video line time Ty-1, each column memory further having sequencing means that couple the information shifted into output bits of the column shift registers at the end of a video line time Ty-1, to the information output of the corresponding column, for each output bit during a different part Ci of the video line time Ty, i being one of the numbers 1 through s inclusive with s being a number that is at least equal to m.
1 Assignment
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Accused Products
Abstract
Control circuit for memory type matrix display with k columns and r rows for k times r display elements, wherein each display element can have one of 2m brightness levels. This control circuit has a video memory for storing brightness information for the display element of each column. It comprises a column memory for each column. Each column memory including m column shift registers. Each column shift register having an input coupled to a corresponding information input for that column, and an output. A line time shift signal Cs being applied to the shift pulse input of all column shift registers for shifting all column shift registers substantially at the end of each line time. The m output bits thus obtained are sequenced by means of a controlled gate circuit to produce a sequence of output bits at the information output of that column. This gate circuit is controlled such that each output bit lasts a predetermined part of the subsequent video line time.
17 Citations
5 Claims
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1. Matrix control circuit for a memory-type visual display with k column inputs and r row inputs for k times r display elements comprising:
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an m-bit serial digital video input receiving a signal defining sequentially one out of 2m brightness levels for each display element of a row y (y=1, 2, . . . , r) of display elements during successive video line times Ty-1 within a frametime that is at least equal to r times a video line time; a series-parallel converter connected to the digital video input, having k times m column outputs corresponding to m bits for each column; a video memory for storing column brightness information, having k times m information inputs which are coupled to the corresponding outputs of the series-parallel converter and k information outputs connected to the k corresponding column inputs of the display; a Y-selection circuit having r selection outputs connected to the corresponding r row inputs of the display, the Y-selection circuit providing (M+1) selection pulses to each row of the display for setting or resetting the memory-type display elements of that row; a timing circuit having at least one clock signal output for supplying a clock signal to clock signal inputs of the video memory and of the Y-selection circuit and a reset signal output for supplying a reset signal to reset signal inputs of the video memory and of the Y-selection circuit; said video memory comprising a number of k column memories, each having a number of m column shift registers of respectively bj bits (j=1, 2, . . . , m), each column shift register having an input that is coupled to the corresponding information input for the corresponding column, a column shift register output and a line time shift signal input for a line time shift signal shifting all column shift registers substantially at the end of each video line time Ty-1, each column memory further having sequencing means that couple the information shifted into output bits of the column shift registers at the end of a video line time Ty-1, to the information output of the corresponding column, for each output bit during a different part Ci of the video line time Ty, i being one of the numbers 1 through s inclusive with s being a number that is at least equal to m. - View Dependent Claims (2, 3, 4, 5)
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Specification