Multiprocessor system

• US 4,672,535 A
• Filed: 03/18/1985
• Issued: 06/09/1987
• Est. Priority Date: 09/07/1976
• Status: Expired due to Term

• Current Assignee: Tandem Computers Incorporated (HP Inc.)
• Original Assignee: Tandem Computers Incorporated (HP Inc.)
• Inventors: Green, Michael D., Wierenga, Steven W., Bartlett, Joel F., Mackie, David R., McEvoy, Dennis L., Katzman, James A., Treybig, James G., Hayashi, Steven J., Bixler, Richard M., Despotakis, John A., Davidow, William H., Greig, David A., Graziano, Peter J.
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US06/713,583
• Time in Patent Office: 813 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/38
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 11/2023 Failover techniques
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 12/1458 by checking the subject access rights
• CPC Class Codes: G06F 13/122 where hardware performs an I/O function other than control of data transfer
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 13/366 using a centralised polling arbiter
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: G06F 7/78 : for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor

Abstract

In a multiprocessor system of the type in which two or more separate processor modules are connected by an interprocessor bus dedicated exclusively to interprocessor communication for parallel processing, there is provided an input/output system having multiported device controllers connected to the multiprocessor system by input/output buses. Each device controller is shared by pairs of the processor modules, and includes logic that ensures that only one port is selected for access at a time.

Claims

1. An input/output system for a multiprocessor system of the kind in which a plurality of separate processor modules are interconnected for processing, each of the processor modules having a central processing unit and an associated main memory, at least a pair of the processor modules each having an input/output channel with each such channel being independent of other such channels, the input/output system comprising:

a device controller for controlling the transfer of data between the pair of processor modules and a peripheral device, the device controller having multiple ports, with each such port being failure-independent of the other such ports and connected to a respective one of said input/output channels, each port including an enable latch operable in response to a disable command communicated to the port by the associated processor module to disable the port from any further data communication;

the device controller including interface logic means responsive to signaling from a one of the processor modules for selecting one of the ports to the exclusion of the other of the ports for data transfers between the peripheral device and the one processor module connected to the selected port through its associated input/output channel; and

interprocessor bus means communicating the pair of processor modules to one another for data transfer therebetween;

each of of processor modules being operable to provide a data communication path to the peripheral device for itself and for the other of the pair of processor modules.

2. The invention defined in claim 1, including a plurality of device controllers each having a plurality of ports respectively coupled to an associated input/output channel of the processor modules, and wherein the ports of each device controller and related system components are constructed so that the ports of one device controller are logically and physically independent of each other and wherein no component part of one port is also a component of the other port of a particular device controller so that no single component failure in one port of a device controller can simultaneously affect the operation of the other port thereof.

3. The invention defined in claim 2, the multiprocessor system including failure detection means comprising means in each of the processor modules for signalling that a particular port no longer operatively connects the device controller to the multiprocessor system.

4. The invention defined in claim 3, each device controller including logic means responsive to receipt of a take ownership signal at a one of the multiple ports to cause the one port to operatively connect the device controller to the multiprocessor system in response to the determination of the failure of another one of the multiple ports.

5. The invention defined in claim 3, wherein each processor module has its own input/output control table in the memory of that processor module for all of the device controllers connected to that processor module and accessible by the input/output channel but not by a device controller so that a single failure on any device controller cannot destroy data in the memory of any processor module connected to that particular device controller.

6. The invention defined in claim 1, including a contorl logic means in the device controller, operable in response to signaling from a one or the other of the processor modules to assume a state that establishes a control connection between the control logic means of the device controller and one of the multiple ports so that only one port has control of the device controller at any one point in time.

7. The invention defined in claim 1, including an input/output control table in the memory of each processor module and containing a first entry defining a buffer area in the memory of each processor module, a second entry defining a buffer area in the memory for a particular device controller, and a third entry specifying the remaining byte count length to be transferred for each peripheral device attached to the input/output channel of that processor module.

8. The invention defined in claim 7, including an error field in each of the first, second, and third entries comprising a plurality of bits indicative of any one of a plurality of numbered errors.

9. The invention defined in claim 6, including a field in each of the first, second, and third entries having a bit which can be set in response to an error encountered during a reconnect and data transfer sequence to specify that the buffer area in memory may be read from but not written into to thereby protect the memory from a failure in the device controller.

10. The invention defined in claim 1, including a plurality of separate power supply means distributed and operatively associated with the processor modules and the device controller and wherein the device controller has two separate and independent power supply means.

11. The invention defined in claim 10, wherein the separate power supply means are distributed and operatively associated with the processor modules and the device controller so that any individual processor module or the device controller can be powered off without affecting continued operation of the rest of the multiprocessor system.

12. The invention defined in claim 10, including a plurality of device controllers, and wherein a plurality of separate power supply means are operatively associated with each device controller so that if one power supply means associated with a device controller becomes inoperative another power supply means takes over to prevent loss of that device controller.

13. The invention defined in claim 12, including diode switch means for connecting two power supply means to each device controller so that each power supply means provides power to such device controller at all times and wherein it one power supply means fails the other power supply means provides all the power to the controller to prevent a discontinuity of power provided to the device controller.

14. An input/output system for a multiprocessor system of the kind in which a plurality of separate processor modules are interconnected for parallel processing, said input/output system comprising:

a plurality of device controllers each having a peripheral device coupled thereto, for controlling the transfer of data between a corresponding ones of the processor modules and the associated peripheral device;

multiple ports in each device controller and multiple input/output buses for connecting each said port to a corresponding processor module for access by a corresponding one of the plurality of processor modules;

each device controller having an interface common logic means operatively associated with the multiple ports of such device controller for insuring that only one port operatively connects the device controller to said multiprocessor system at a time; and

said device controllers being connected in a star poll with at least one processor module by a multibit data bus and being divided into ranks of a plurality of groups and wherein groups are assigned relative priority among themselves and priority is also assigned among the device controllers within each group, and a priority resolve means in at least one processor module for determining which device controller has the highest priority within each group for connecting to the at least one process module the highest priority device controller making a reconnect request.

15. An input/output system for a multiprocessor system of the kind in which a plurality of separate processor modules are interconnected for parallel processoring, each of said processor modules having a central processing unit and a memory, each of the processor modules having an input/output channel, said input/output system comprising:

a plurality of device controllers, each having at least one peripheral device coupled thereto, for controlling the transfer of data between ones of the processor modules and the corresponding peripheral device;

multiple ports in each device controller and multiple input/output buses for connecting each of the ports of each device controller for access by multiple different processor modules;

interface common logic means operatively associated with each device controller for insuring that only one port operatively connects the device controller to said multiprocessor system at a time;

the memory of each processor module includes an input/output control table containing an entry which defines a buffer area in the memory for a particular device controller and a entry specifying the remaining byte count length to be transferred for each peripheral device attached to the input/output channel of that processor module; and

means causing the input/output channel of a corresponding processor module, in response to a reconnect request to that processor module by a device controller associated with that input/output channel when a count word in the input/output control table thereof is a predetermined count, to go to an abort state to protect the memory of that processor module from being overwritten by the associated failing device controller.

16. An input/output system for a multiprocessor system of the kind in which separate processor modules are interconnected for parallel processing, said input/output system comprising:

at least one device controller for controlling the transfer of data between a processor module and a peripheral device;

multiple ports in each device controller and multiple input/output buses for connecting each device controller for access by multiple different processor modules;

each device controller having interface common logic means for insuring that only one of the multiple ports operatively connects the corresoplnding device controller to said multiprocessor system at a time;

a plurality of separate power supply means distributed and operatively associated with the process modules and the device controllers wherein each device controller has two separate and independent power supplies, the separate power supplies being connected so that any individual processor module or device controller can be powered off without affecting continued operation of the rest of the multiprocessor system an online maintenance can be performed on any individual processor module or device controller by powering down that processor module or device controller while the rest of the multiprocessor system is on-line and functional; and

the device controller including power-on circuit means for sensing if power is within acceptable operating limits and for defining the operation of the device controller as power is turned on or off to protect the associated input/output bus from erroneous signals and to permit on-line maintenance.

17. The invention defined in claim 16, including interface devices in each port for driving the input/output buses and wherein the power-on circuit means coact with the interface devices during a failure or turn-off of an associated power supply to electrically prevent the interface device from driving the input/output bus to thereby prevent one device controller from contaminating the input/output bus during a failure or turn-off of a power supply.

18. An input/output system for a multiprocessor system of the kind in which separate processor modules are interconnected for parallel processing, each of said processor modules having a central processing unit and a memory, at least some of the processor modules having an input/output channel, said input/output system comprising:

device controller means for controlling the transfer of data between a processor module and a peripheral device;

multiple ports in the device controller means and multiple input/output buses for connecting ports of each device controller for access by multiple different ones of the processor modules;

interface common logic means operatively associated with each device controller, responsive to signaling from a one of the process modules, for insuring that only port operatively connects the device controller to said multiprocessor system at a time; and

each device controller including buffer means for momentarily holding information for indicating the direction of data transfer to and from an input/output bus and the degree of full or empty condition of a buffer of said buffer, means the buffer means of each device controller including hold-off depth logic operable to delay for a certain amount of time after each input/output channel disconnection and before making a subsequent reconnect request to thereby allow lower priority devices access to the input/output channel.

19. The invention defined in claim 18, wherein the buffer means further includes threshold logic means operably coupled to the hold-off depth logic for determining the remaining depth of the buffer means.

20. The invention defined in claim 19, wherein the hold-off depth logic is operable to delay data transfer long enough to permit lower priority device controllers to be serviced before making another reconnect request.

21. In a multiporcessor system of the type including a plurality of separate processor modules that are interconnected by an interprocessor bus means for processing and information communication therebetween, at least a pair of the processor modules each having an input/output channel with each such channel being independent of other such channels, the input/output system comprising:

a plurality of device controllers, each operable to control the transfer of data between the pair of processor. modules and peripheral device connected to each of the plurality device controller, each of the device controllers having multiple ports, each port including enabling means responsive to a disable command from the processor module associated with said port to disable the port from further data communication;

input/output bus means coupling the input/output channel of each of the pair of processor modules to a corresponding one of the ports of each of the device controllers;

each of the device controllers including interface logic means responsive to signaling from the processor modules for selecting one of the ports to the exclusion of the other of the ports for data transfers between an associated one of the peripheral devices and the one processor module connected to the selected port through its associated input/output channel; and

each of the pair of processor modules being operable to provide a data communication path to the peripheral device for itself and for the other of the pair of processor modules.