PBX telephone system I/O interface

• US 4,674,082 A
• Filed: 10/31/1986
• Issued: 06/16/1987
• Est. Priority Date: 10/05/1982
• Status: Expired due to Term

• Current Assignee: Shared Technologies Fairchild Telecom, Inc.
• Original Assignee: Telex Computer Products Incorporated
• Inventors: Flanagin, Stephen D., Scantlin, John R., Bubb, Howard G.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): KUNTZ, CURTIS A
• Application Number:
  US06/926,815
• Time in Patent Office: 228 Days
• Field of Search: 370/94, 370/60, 370/58, 370/85, 370/68, 370/67, 340/825.5
• US Class Current: 370/355
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence

Abstract

Apparatus is provided for converting serial bit digital signals of selected line rate from a plurality of sources into a single serial bit signal for time division multiplexing (TDM) in periodic frames by a central receiver, in a system in which each source is responsive to command signals for transmitting signal information to the receiver.

Claims

1. Input/output (I/O) interface apparatus for use with a time slot interchange (TSI) matrix switch which exchanges serial bit signal packets in each sample frame of a source sample frequency with N number of asynchronous signal sources, at a source line frequency, comprising:

plurality of signal ports, one signal port associated with each signal source, for receiving and transmitting the signal packets between the TSI matrix switch and the associated source;

timing means for providing a clock signal having a clock frequency at least 2 times higher in frequency than the source line frequency and having a clock time period;

program control means, responsive to said clock signal and to each of the n number of sources, for regulating the length of a real time interval between the time of arrival (TOA) and the time of departure (TOD) of the signal packets at each said signal port in dependence on the source line frequency and for regulating the actual TOA and actual TOD of the signal packets at each said port in dependence on said clock frequency; and

signal transfer means responsive to said clock signal and to said actual TOA and said actual TOD of the signal packets at each said port, for exchanging the serial bit signals of each signal packet between each said signal port and the TSI matrix switch at a signal bit line frequency substantially equal to said clock frequency.

2. The apparatus of claim 1, wherein said signal transfere means comprises:

multiplexing means, responsive to said clock signal and to said actual TOA of the signal packets received from the N number of signal sources in each sample frame at each said port, for sampling the N signal packets in a plurality of successive input segment signals equal in number to the number of bits in the signal packets, each said input segment comprising single bit samples from each of the N signal packets, said single bit samples arranged serially at said bit line frequency, successive segments occurring at a segment frequency substantially equal to the source line frequency, and for presenting said input segments in real time to the TSI matrix switch; and

demultiplexing means, responsive to said clock signal and to said actual TOD of the signal packets from each said port, for demultiplexing a plurality of output segment signals received from the TSI in each sample frame at said segment frequency and said bit line frequency, into N number of individual signal packets, said demultiplexing means presenting successive bits of each said output segment signal to successive ones of said signal ports at spaced real time intervals substantially equal to said clock time period.

3. A method for exchanging serial bit signal packets between N number of asynchronous signal sources and a time slot interchange (TSI) matrix switch in each sample frame of a source sample frequency, each signal packet including M number of serial signal bits at a source line frequency, comprising the steps of:

designating N number of signal ports, one signal port associated with each signal source, for receiving and transmitting the signal packets between the TSI matrix switch and the associated source;

providing a clock signal at a clock frequency at least N times higher in frequency than the source line frequency, and having a clock time period;

controlling, in each sample frame, the time of arrival (TOA) of the signal packet received at each said signal port from the associated signal source and the time of departure (TOD) of the signal packet transmitted from each said signal port to the associated source, such that the actual TOA and the actual TOD of the signal packets or preceding and succeeding signal ports, in an operator selected sequence of said signal ports, are spaced at real time intervals substantially such that the length of a real time interval between the actual TOA and the acutal TOD of the signal packets of each said signal port is set in dependence on said source line frequency; and

transferring the serial bits of each signal packet between each said signal port and the TSI matrix switch at a signal bit line frequency substantially equal to said clock frequency.

4. The method of claim 3, wherein the step of transferring comprises the steps of:

multiplexing the N number of signal packets received at said signal ports in each sample frame into M number of successive input segment signals corresponding in number to the M number of signal bits in the signal packets, each input segment signal comprising single bit samples from each of the N signal packets, said single bit samples arranged serially at said bit line frequency and successive ones of said N input segment signals occurring at a segment frequency substantially equal to the source line frequency and presenting said input segment signals in real time to the TSI matrix switch; and

demultiplexing M number of output segment signals received from the TSI matrix switch in each sample period at said segment frequency and said bit line frequency, into N signal packets by presenting successive bits of each said output segment signal to successive ones of said signal ports at spaced real time intervals substantially equal said clock time period.