Token ring access control protocol circuit

• US 4,674,086 A
• Filed: 12/16/1985
• Issued: 06/16/1987
• Est. Priority Date: 12/16/1985
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hubbins, Stephen, Szczepanek, Andre
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Rokoff, Kenneth I.
• Application Number:
  US06/809,626
• Time in Patent Office: 547 Days
• Field of Search: 370/86, 370/89, 370/90, 340/825.05
• US Class Current: 370/452
• CPC Class Codes: H04L 12/433 with asynchronous transmission, e.g. token ring, register insertion

Abstract

A token ring access control protocol circuit which includes an M/T converter for converting incoming serial data in differential Manchester encoded form into transitional encoded form. Next the data is fed into a shift register and held temporarily while it is compared with preset sequences to determine if it is a starting delimiter or an ending delimiter. If a starting delimiter pulse is generated and used to synchronize subsequent circuitry if required. Data from the shift register is continuously sampled with at least a 2 baud delay by a data sample latch circuit which provides and output line for data values and another output line for code violation signals. The data values and code violation values go to a data receiving circuit which processes the data, and loads it onto a local data bus for transmission to other parts of a token ring control system. A data insertion multiplexer has inputs which are connected to the serial data output of the shift register, the output of the transmit machine and to various state machines for inserting modified data into the serial data path. The output of the data insertion multiplexer goes both to a transmit output multiplexer and to a fairness delay.

Claims

1. A token ring access control protocol circuit having a token/frame transmission path and a processor, said token/frame transmission path comprising:

a M/T converter for converting input serial data stream to a selected encoding;

an BCLK baud clock signal source derived from an incoming data stream;

means for temporarily serially storing incoming data and detecting incoming tokens/frames, coupled to said BCLK source for clocking the data into and out of said storing means;

data sampling means coupled to said storing means for sampling data bauds and code violation bauds from data bauds of tokens/frames stored therein and for transmitting said data and code violation bauds to said processor;

data modification means coupled to said storing means for reading data bauds out of and writing data bauds into a token/frame, bauds of which are stored in said storing means;

data multiplexing means coupled to said storing means for reading data bauds out of and writing data bauds into a token/frame, bauds of which are stored in said storing means;

data multiplexing means coupled to said storing means for transmitting one of a plurality of inputs therefrom in accordance with control signals from said processor;

fairness means coupled to said path for examining passing tokens and to modify them in accordance with a fairness algorithm in response to release of a token and to control signals from said processor;

wherein said data sampling and modification means are coupled to circuitry for

(i) monitoring passing tokens/frames, recording their status, marking them and deleting them;

(ii) examining the addresses of incoming tokens/frames and copying those with appropriate addresses, signaling the return of transmitted frames to said processor; and

(iii) examining incoming tokens and determining those which can be used to transmit tokens/frames and, in response to control signals from said processor, to transmit tokens.

2. A token ring protocol circuit according to claim 1, wherein said data storing means includes a shift register coupled to the output of said M/T converter for holding a serial block of data of a predetermined number of bauds and a decoder coupled to said shift register for continuously comparing data bauds therein to a preset sequence of reference values and, upon detection of a predetermined starting delimiter sequence of bauds, generating a starting delimiter pulse for use in synchronizing subsequent circuitry and upon detecting a predetermined ending delimiter sequence of bauds generating an ending delimiter pulse for input to said processor.

3. A token ring protocol circuit according to claim 2, wherein said data modification means includes a data insertion multiplexer coupled to said shift register for receiving serial data signals therein, a transmit data input coupled to said processor and a plurality of data modification input coupled to said processor for inserting modified data into said serial data path.

4. A token ring protocol circuit according to claim 3, including an elastic buffer coupled to an output of said fairness means for absorbing phase jitter and drift in the incoming data stream and clocking the data out by a fixed baud clock XCLK.

5. A token ring protocol circuit according to claim 4, including a transmit output multiplexer having inputs coupled to an output of said data insertion multiplexer, an output of said fairness means and an output of said elastic buffer and responsive to a control sigal from said processor to transmit to its output a selected one of its inputs.

6. A token ring protocol circuit according to claim 4, including a monitor delay coupled to said transmission path for inserting a predetermined delay in said serial data path in response to a monitor control signal.

7. A token ring protocol circuit according to claim 6, wherein said monitor delay includes a first monitor delay coupled to an output of said fairness circuit and a second monitor delay coupled to an output of said elastic buffer, said first monitor delay being sufficiently long to allow deletion of starting delimiters from defective tokens and a second monitor delay coupled to an output of said elastic buffer of sufficient delay to allow said elastic buffer to be cleared before a frame being transmitted thereby returns.

8. A token ring protocol circuit according to claim 7, wherein said incoming data stream is in Manchester encoded form and said M/T converter converts incoming data to transitional encoded form.

9. A token ring access control protocol circuit having a token/frame transmission path and a processor for controlling data flow in said path and for handling data and transmitting data along said path, said token/frame transmission path comprising:

a M/T converter for converting a Manchester encoded input serial data stream to transitional encoding;

a shift register coupled to an output of said M/T converter for holding a serial block of data of a predetermined number of bauds;

a decoder coupled to said shift register for continuously comparing data bauds in said shift register to a preset sequence of reference values and, upon detection of a predetermined starting delimiter sequence of bauds, generating a starting delimiter pulse for use in synchronizing subsequent circuitry and upon detecting a predetermined ending delimiter sequence of bauds generating an ending delimiter pulse;

a data sample latch circuit having an input coupled to said shift register and decoder for sampling data at least two bauds downstream of said shift register input and having one output for data values and another for corresponding code violation values, said outputs coupled to said processor;

a data insertion multiplexer having a repeat data input coupled to said shift register for receiving serial data signals thereon, a transmit data input coupled to a data transmitting circuit and a plurality of data modification inputs coupled to respective state machines in said processor for inserting a modified data into the serial data path;

a fairness circuit having an input coupled to an output of said data insertion multiplexer and responsive to a fairness control signal to delay the incoming data stream and to examine and modify passing tokens in accordance with a preselected fairness algorithm;

a monitor delay coupled to said transmission path for inserting a predetermined delay in said serial data path in response to a monitor control signal;

an elastic buffer coupled to an output of said monitor delay having a plurality of serial data baud register cells and control means for adjusting the number of such cells between a cell into which a data baud is being stored and a cell out of which a data baud is being directed so as to absorb phase jitter or drift in said incoming serial data signal;

a transmit output multiplexer coupled to an output of said token/frame transmission path; and

a T/M converter coupled to an output of said transmit output multiplexer for converting transitional encoded data to Manchester encoded data.

10. A token access control protocol circuit according to claim 9, wherein said monitor delay includes a first monitor delay coupled to an output of said fairness circuit for delaying tokens/frames sufficiently long to permit said processor to remove a starting delimiter from a defective token/frame and a second monitor delay coupled to an output of said elastic buffer for delaying tokens/frames sufficiently long to permit said buffer to clear before the token/frame can return to said elastic buffer.

11. A token ring access control protocol circuit according to claim 10, wherein said first monitor delay is 7.5 bauds and said second monitor is 24.5 bauds.

12. A token ring protocol circuit according to claim 9, wherein said data sample latch circuit is coupled to a second baud of said shift register.

13. A token ring protocol circuit according to claim 9, wherein said processor is clocked by a bit clock derived from a baud rate clock supply BCLK.