In-circuit emulator

• US 4,674,089 A
• Filed: 04/16/1985
• Issued: 06/16/1987
• Est. Priority Date: 04/16/1985
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: McKinley, Jeanne, Poret, Mark
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): Beausoliel, Jr., Robert W.
• Application Number:
  US06/723,739
• Time in Patent Office: 791 Days
• Field of Search: 371/16, 371/18, 371/19, 371/24, 371/25, 364/200, 364/900, 324/73 R
• US Class Current: 714/28
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

A circuit is disclosed which is implemented on the same silicon chip as a microprocessor to be utilized in a microprocessor system such as a microcontroller, which circuit allows a user to perform in-circuit emulation ("ICE") for the purpose of debugging the microprocessor system. The ICE circuitry comprises (i) capture logic which monitors the contents of the program address register and the internal data bus and various control lines of the processor; (ii) trace circuitry comprising a FIFO buffer which puts data from the capture logic to the output pins of the chip; and (iii) a content addressable memory and a software programmable logic array with emulation counters which together function as a finite state machine which performs the desired predetermined testing of the system.

Claims

1. An integrated circuit in-circuit emulator for testing a microprocessor system including at least one microprocessor which forms a portion of said integrated circuit comprising:

capture logic means including a plurality of latches coupled to a program counter, internal data bus and control lines disposed within said microprocessor and to an address and data bus of said microprocessor, which latches store the data from said program counter, internal data bus, address and data bus and control lines, each clock cycle of said microprocessor, said capture logic means for storing predetermined data in a memory and comparing said predetermined data with said stored data generated by said microprocessor and generating an output signal whose value depends on the results of said comparison;

comparison means including a content addressable memory and at least one comparator for storing predetermined data in a memory and comparing said predetermined data with said stored data generated by said microprocessor and generating an output signal whose value depends on the results of said comparison;

logic means for receiving said output signal and selectively generating a trace signal and break signal depending upon the value of said output signal, wherein said content addressable memory is coupled to said logic means and stores said predetermined data, and said at least one comparator is coupled to said plurality of latches for comparing at least one of the opcode, program counter address, source address, destination address, address space and data of instructions executed by said microprocessor with a corresponding field of a memory location within said content addressable memory;

means for selectivily enabling said data generated by said microprocessor to be available externally to said integrated circuit depending upon the value of said trace signal; and

means for controlling the mode of operation of said emulator depending upon the value of said break signal.

2. The emulator defined by claim 1 wherein said at least one comparator includes at least one mask register for forcing the matching of bits stored in said comparator, the value stored in said mask register being determined by a corresponding field of a memory location within said content addressable memory.

3. The emulator defined by claim 1 wherein said logic means comprises a programmable logic array.

4. The emulator defined in claim 3 wherein said programmable logic array is software programmable.

5. The emulator defined by claim 1 wherein said enabling means comprises a trace buffer coupled to said capture logic means for buffering data stored in said capture logic means for output to an external memory.

6. The emulator defined by claim 1 wherein said controlling means selectively places said emulator in one of an emulation mode, interrogation mode and halt mode.

7. The emulator defined by claim 1 wherein said at least one comparator includes a magnitude comparator coupled to a destination address register, said magnitude comparator for comparing an actual destination address of an instruction being executed with a destination address stored in said destination address register, and generating a signal when a predetermined match condition is met.

8. The emulator defined by claim 1 wherein said at least one comparator includes a magnitude comparator coupled to a program counter register, said magnitude comparator for comparing an actual program counter address for an instruction being executed with a program counter address stored in said program counter register, and generating a signal when a predetermined match condition is met.

9. The emulator defined by claim 1 wherein said at least one comparator includes an equality comparator coupled to an opcode register, said equality comparator for comparing an opcode stored in said opcode register with an opcode of an instruction being executed, and generating a signal if a predetermined match condition is met.

10. The emulator defined by claim 1 wherein said at least one comparator includes an equality comparator coupled to a data register, said equality comparator for comparing the data value stored in said data register with the data field of an instruction being executed and generating a signal if a predetermined match condition is met.

11. The emulator defined by claim 1 wherein said at least one comparator includes a magnitude comparator coupled to a program counter register and destination address register, and an equality comparator coupled to an opcode register and a data register, said magnitude comparator for comparing values in one of said program counter register and destination address register with corresponding fields in an instruction being exeucted and generating a signal if a predetermined match condition is met, said equality comparator coupled to an opcode register and a data register for comparing values in one of said opcode register and data register with corresponding fields in an instruction being executed, and generating a signal if a predetermined match condition is met.