Digital signal processor

• US 4,674,105 A
• Filed: 02/26/1985
• Issued: 06/16/1987
• Est. Priority Date: 03/02/1984
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Suzuki, Hideo
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Huseman, M.
• Application Number:
  US06/705,530
• Time in Patent Office: 840 Days
• Field of Search: 375/39, 375/78, 375/80, 375/81, 375/83, 375/86, 375/88, 375/90, 329/50, 329/104, 329/105, 329/110, 329/145, 370/20
• US Class Current: 375/324
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/22 Demodulator circuits; Receiver circuits

Abstract

A digital signal processor for performing phase or frequency signal processes, for example, demodulating processes of modulation signals such as PSK signals. This processor is provided with amplitude-to-phase converting means which receives two digital input signal series that are respectively expressed by a plurality of bits and that have a quadrature phase relation with each other, and which outputs the digital phase information signal corresponding to a combination of the digital values of those input signal series, this combination being amplitude information. This processor then supplies the phase information signal which is outputted from the amplitude-to-phase converting means to signal processing means, thereby digitally processing the phase information signal.

Claims

1. A digital signal processor comprising:

amplitude-to-phase converting means which receives two modulated digital input signal series that are respectively expressed by a plurality of bits and that have a quadrature relation and which outputs a digital phase information signal corresponding to a combination of digital values of said input signal series, said digital values being amplitude information;

means for generating a digital reference signal;

means for generating, as a digital signal, a phase difference signal indicative of the difference between the phase information which is given due to said digital reference signal and the phase information which is given due to the phase information signal which is outputted from said amplitude-to-phase converting means;

means for outputting a demodulation signal on the basis of said phase difference signal; and

means for controlling said reference signal on the basis of said phase difference signal.

2. A digital signal processor according to claim 1, wherein said amplitude-to-phase converting means includes a ROM table which stores the phase information as the digital values corresponding to all combinations of the digital values of said input signal series.

3. A digital signal processor according to claim 1, wherein said amplitude-to-phase converting means includes:

a ROM table which stores the phase information as the digital values corresponding to all combinations of the digital values of said input signal series in a partial quadrant of a phase plane where said input signal series exist;

quadrant judgment means for discriminating the quadrant in said phase plane corresponding to the combination of the digital values of said input signal series and outputting predetermined digital values corresponding to the result of said discrimination; and

means for synthesizing the digital values which are outputted from said ROM table and the digital values which are outputted from said quadrant judgment means, thereby outputting the digital phase information signal corresponding to the combination of the digital values of said input signal series.

4. A digital signal processor according to claim 1, wherein said means for outputting a demodulation signal by adding said phase difference signal and predetermined constant phase information which is given as a digital signal.

5. A digital signal processor comprising:

amplitude-to-phase converting means which receives two modulated digital input signal series that are respectively expressed by a plurality of bits and that have a quadrature relation and which outputs a digital phase information signal corresponding to a combination of digital values of said input signal series, said digital values being amplitude information;

means for generating a digital reference signal;

means for outputting, as a digital signal, a phase difference information signal indicative of the difference between the phase information which is given due to the phase information signal which is outputted from said amplitude-to-phase converting means and the phase information which is given due to said reference signal;

means for outputting a demodulation signal by discriminating signs of the original data of said modulation signals on the basis of said phase difference signal;

means for outputting, as a digital signal, a reproduced modulation waveform signal corresponding to the phase information which is given due to the phase information signal which is outputted from said amplitude-to-phase converting means on the basis of said demodulation signal; and

means for controlling said reference signal on the basis of said reproduced modulation waveform signal.

6. A digital signal processor according to claim 5, wherein said amplitude-to-phase converting means includes a ROM table which stores the phase information as the digital values corresponding to all combinations of the digital values of said input signal series.

7. A digital signal processor according to claim 5, wherein said amplitude-to-phase converting means includes:

a ROM table which stores the phase information as the digital values corresponding to all combinations of the digital values of said input signal series in a partial quadrant of a phase plane where said input signal series exist;

quadrant judgment means which discriminates the quadrant in said phase plane corresponding to the combination of the digital values of said input signal series and which outputs predetermined digital values corresponding to the result of said discrimination; and

means which synthesizes the digital values which are outputted from said ROM table and the digital values which are outputted from said quadrant judgment means, thereby outputting the digital phase information signal corresponding to the combination of the digital values of said input signal series.

8. A digital signal processor according to claim 5, wherein said means for outputting the demodulation signal differentiate said phase difference signal with respect to time.

9. A digital signal processor according to claim 5, wherein said means for outputting said reproduced modulation waveform signal includes a wave memory in which modulation signal waveform information corresponding to the phase information which is given due to the phase information signal that can be outputted from said amplitude-to-phase converting means has been preliminarily stored as digital values and which is accessed due to the information content for a predetermined constant interval of said demodulation signal.

10. A digital signal processor according to claim 9, wherein said means for outputting said reproduced modulation waveform signal further includes means for accumulating an output signal from said wave memory.

11. A digital signal processor according to claim 5, wherein said means for controlling said reference signal includes:

means for outputting a difference signal between said phase difference signal and said reproduced modulation waveform signal; and

means for controlling said reference signal such that said difference signal is minimized.

12. A digital signal processor according to claim 5, wherein said means for controlling said reference signal includes:

means for modulating said reproduced modulation waveform signal with said reference signal;

means for outputting a difference signal between a modulation signal which is outputted from said modulating means and the phase information signal which is outputted from said amplitude-to-phase converting means; and

means for controlling said reference signal such that said difference signal is minimized.

13. A digital signal processor according to claim 5, wherein said means for controlling said reference signal includes:

means for modulating the phase information signal which is outputted from said amplitude-to-phase converting means with said reproduced modulation waveform signal;

means for outputting a difference signal between a signal which is outputted from said modulating means and said reference signal; and

means for controlling said reference signal such that said difference signal is minimized.