EPROM programmer
First Claim
1. In an EPROM programmer havinga sheet reading device defining a path along which a program sheet passes, the program sheet bearing write clock marks, an R/W line for controlling reading and writing functions, and data lines, the sheet reading device being arranged to generate write clock pulses, an R/W signal, and data output corresponding to the respective marks and lines on the program sheet,a RAM for memorizing said data output in synchronism with said write clock pulses,an EPROM detachably mounted on a connector,first means for generating read clock pulses,a binary counter for counting said clock pulses and for addressing said RAM and EPROM,a first gate means responsive to a first mode of said R/W signal to render said RAM in a write state and responsive to a second mode of said R/W signal to change said RAM to a read state for writing the data stored in the RAM into the EPROM,a second gate means for generating and end signal for stopping the reading operation when the count of said binary counter reaches a predetermined number,the improvement comprising:
- a ring counter responsive to the end signal from the second gate means for sequentially producing an erase check mode signal for checking the initialized state of the EPROM, a write mode signal for writing the data into the RAM, a program mode signal for programming the EPROM, and a verify check mode signal for verifying the data programmed into the EPROM;
a third gate means responsive to the erase check mode signal for addressing the EPROM;
second means for checking the outputs of the EPROM in response to the addressing by said third gate means for determining whether the EPROM is normal and for indicating when the EPROM is abnormal, and for resetting the ring counter upon such indication; and
comparing means responsive to the verify check mode signal for comparing the data in the EPROM with the data in the RAM and for indicating when the former data do not coincide with the latter, and for resetting the ring counter upon such indication.
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Abstract
When supply voltage is first supplied to an EPROM programmer, the system is placed in an erase check mode. An EPROM is attached to the device, and an erase check switch is depressed. If there is no abnormality in the EPROM, a ring counter operates to change the system to a write mode. A program sheet is inserted into the device from one side up to a predetermined position and taken out from the other side. After that, writing data into a RAM, programming of the EPROM dependent on the data in the RAM, and verify checking of the programmed EPROM are sequentially operated automatically by output signals from the ring counter. If an abnormality is detected in the erase check mode or verify check mode, the abnormality is indicated and the ring counter is reset to return the initial state. Thus, the EPROM can be replaced for re-programming operation.
14 Citations
3 Claims
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1. In an EPROM programmer having
a sheet reading device defining a path along which a program sheet passes, the program sheet bearing write clock marks, an R/W line for controlling reading and writing functions, and data lines, the sheet reading device being arranged to generate write clock pulses, an R/W signal, and data output corresponding to the respective marks and lines on the program sheet, a RAM for memorizing said data output in synchronism with said write clock pulses, an EPROM detachably mounted on a connector, first means for generating read clock pulses, a binary counter for counting said clock pulses and for addressing said RAM and EPROM, a first gate means responsive to a first mode of said R/W signal to render said RAM in a write state and responsive to a second mode of said R/W signal to change said RAM to a read state for writing the data stored in the RAM into the EPROM, a second gate means for generating and end signal for stopping the reading operation when the count of said binary counter reaches a predetermined number, the improvement comprising: -
a ring counter responsive to the end signal from the second gate means for sequentially producing an erase check mode signal for checking the initialized state of the EPROM, a write mode signal for writing the data into the RAM, a program mode signal for programming the EPROM, and a verify check mode signal for verifying the data programmed into the EPROM; a third gate means responsive to the erase check mode signal for addressing the EPROM; second means for checking the outputs of the EPROM in response to the addressing by said third gate means for determining whether the EPROM is normal and for indicating when the EPROM is abnormal, and for resetting the ring counter upon such indication; and comparing means responsive to the verify check mode signal for comparing the data in the EPROM with the data in the RAM and for indicating when the former data do not coincide with the latter, and for resetting the ring counter upon such indication. - View Dependent Claims (2, 3)
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Specification
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- Resources
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Current AssigneeYoshikazu Kuze
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Original AssigneeYoshikazu Kuze
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InventorsKuze, Yoshikazu
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Primary Examiner(s)Trafton, David L.
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Application NumberUS06/686,905Time in Patent Office908 DaysField of Search235/454, 235/375, 235/380, 235/474, 365/201, 377/46US Class Current235/375CPC Class CodesG11C 16/14 Circuits for erasing electr...G11C 29/56 External testing equipment ...
