Method and apparatus for dynamically controlling the timing of signals in automatic test systems

• US 4,675,562 A
• Filed: 05/17/1984
• Issued: 06/23/1987
• Est. Priority Date: 08/01/1983
• Status: Expired due to Fees

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Davis, Jeffrey A., Herlein, Richard F., Cotriss, E. James
• Primary Examiner(s): Heyman, John S.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US06/611,451
• Time in Patent Office: 1,132 Days
• Field of Search: 328/104, 328/109, 328/137, 328/154, 328/55, 328/56, 307/602, 307/603, 307/605, 307/606, 307/608, 307/595, 307/596, 307/518, 307/243
• US Class Current: 327/277
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/3191 Calibration
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G01R 31/31928 Formatter driver, receiver details G01R31/31924
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24
• CPC Class Codes: H03K 2005/00247 using counters
• CPC Class Codes: H03K 2005/00254 using microprocessors
• CPC Class Codes: H03K 2005/0026 using memories or FIFO's
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence

Abstract

Apparatus for delaying an electrical signal includes a sequence of stages, each for delaying the signal. A coarser stage delays the signal by multiples of a predetermined fundamental delay interval and a finer stage provides for fine adjustment of the delay. The fine stage includes an integral number N of delay elements, the total providing a delay interval greater than the fundamental delay interval, whereby the fine delay intervals compensate for fabrication tolerances to enable accurate calibration of the combined system by post-fabrication measurement. In one implementation each delay stage includes a tapped transmission line to provide delay intervals, in another a ramp generator is used.

Claims

1. Apparatus connected between an input terminal and an output terminal for delaying an electrical signal supplied to the input terminal before supplying it to the output terminal, the apparatus comprising:

first means for delaying signals by a selected multiple of a first nominally predetermined delay interval, the first means connected to the input terminal to receive the electrical signal and delay it by passing it through a delay line to provide a first delayed signal at a first node;

N delay elements, where N is an integer greater than one, each element providing a second nominally predetermined delay interval which is greater than the first nominally predetermined delay interval divided by N, and wherein the N delay elements include a second delay line having a plurality of taps at intervals thereon;

second means connected to the first node to receive the first delayed signal, connected to the output terminal, and connected to the N delay elements, the second means being operable to pass the first delayed signal through a selected series of the N delay elements to thereby further delay the first delayed signal to provide a second delayed signal to the output terminal.

2. Apparatus as in claim 1 wherein the first means comprises:

first multiplexing means having a plurality of input terminals; and

a first transmission line having a plurality of taps at intervals thereon, each tap connected to a successive input terminal of the first multiplexing means.

3. Apparatus as in claim 2 wherein the second means comprises:

second multiplexing means having a plurality of input nodes; and

wherein the N delay elements comprise a second transmission line having the plurality of taps at intervals thereon, each tap connected to a successive input node of the second multiplexing means.

4. Apparatus as in claim 2 wherein the first multiplexing means includes addressable controls for selectively connecting one of the taps on the first transmission line to the first node.

5. Apparatus as in claim 4 wherein the first multiplexing means comprises a first multiplexer including differential input stages, and the first transmission line comprises a differential transmission line connected to the differential input stages.

6. Apparatus as in claim 5 wherein termination means are provided following a last input terminal of the first multiplexer to terminate the first transmission line.

7. Apparatus as in claim 3 wherein the second multiplexing means includes addressable controls for selectively connecting one of the taps on the second transmission line to the output terminal.

8. Apparatus as in claim 1 further comprising:

a set of M delay elements, where M is an integer, each element providing a third nominally predetermined delay interval, which third nominally predetermined delay interval is greater than the second nominally predetermined delay interval divided by M; and

third means connected between the output terminal and the second means to receive the second delayed signal from the second means, and connected to the M delay elements, the third means being operable to pass the second delayed signal through a selected series of the M delay elements and delay it to provide a third delayed signal to the output terminal.

9. Apparatus as in claim 7 wherein:

the third means comprises a third multiplexing means having a plurality of input terminals and at least one third output terminal, and

the set of M delay elements comprises a third transmission line having a plurality of taps at intervals connected to successive input terminals of the thrid multiplexer.

10. Apparatus for delaying an electrical signal comprising:

a first transmission line having M taps along its length, where M is an integer greater than one;

a first multiplexer having M input terminals, each connected to a different one of the M taps, the M taps dividing the first transmission line into M-1 segments, wherein the M taps are positioned to delay an electrical signal passing along the first transmission line by a first predetermined delay interval between successive taps, the first multiplexer providing a first delayed signal at a first multiplexer output terminal;

a second transmission line having N taps along its length, where N is an integer greater than one, the second transmission line being connected to receive the first delayed signal from the first multiplexer output terminal;

a second multiplexer having N input terminals, each connected to a different one of the N taps, the N taps dividing the second transmission line into N-1 segments, wherein the N taps are positioned to delay an electrical signal passing along the second transmission line by a second predetermined delay interval between successive taps, the second multiplexer providing a second delayed signal at a second multiplexer output terminal; and

wherein the delay of the N-1 segments combined is greater than the delay of a single segment of the first transmission line.

12. Apparatus as in claim 10 further comprising control means receptive to data input signals and coupled to each of the ramp generating means and the gate means for controlling both in response to the data input signals.

11. Apparatus for delaying an electrical signal comprising:

first means for delaying signals by a preselected interval, the first means connected to receive the electrical signal and delay it for up to a predetermined delay interval to provide a first delayed signal;

N serially connected delay elements, where N is an integer, coupled to receive the first delayed signal and further delay it by transmitting the first delayed signal through a predetermined number of the N delay elements and supply it to an output terminal; and

wherein the first means comprises ramp generating means and the delay elements comprise gate means.

13. Apparatus connected between an input terminal and an output terminal for delaying an electrical signal supplied to the input terminal before supplying it to the output terminal, the apparatus comprising:

a first delay line having a plurality of fine taps at intervals thereon, the fine taps dividing the first delay line into a series of fine segments, each segment providing a fine nominally predetermined delay interval, all of the series of fine segments of the first delay line together providing a total fine delay period;

fine delay means connected to the input terminal to receive the electrical signal, connected to a first node, and connected to each of the fine taps, the fine delay means being operable to pass the electrical signal through a selected series of the fine segments to delay the electrical signal and thereby provide a first delayed signal at the first node;

a second delay line having a plurality of coarse taps at intervals thereon, the coarse taps dividing the second delay line into a series of coarse segments, each segment providing a coarse nominally predetermined delay interval which is less than the total fine delay period; and

coarse delay means connected to the first node to receive the first delayed signal, connected to the output terminal, and connected to each of the coarse taps, the coarse delay means being operable to pass the first delayed signal through a selected series of the coarse segments to delay the first delayed signal and thereby provide a second delayed signal to the output terminal.